Patents by Inventor HEQUAN JIANG

HEQUAN JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391870
    Abstract: The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.
    Type: Application
    Filed: January 7, 2020
    Publication date: December 16, 2021
    Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.
    Inventors: Daiguo XU, Hequan JIANG, Xueliang XU, Jian'an WANG, Guangbing CHEN, Dongbing FU, Yuxin WANG, Xiaoquan YU, Shiliu XU, Tao LIU
  • Patent number: 10778092
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 15, 2020
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Patent number: 10735018
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 4, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Publication number: 20200195270
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Application
    Filed: June 21, 2017
    Publication date: June 18, 2020
    Inventors: RONGBIN HU, YONGLU WANG, ZHENGPING ZHANG, JIAN'AN WANG, GUANGBING CHEN, DONGBING FU, YUXIN WANG, HEQUAN JIANG, GANGYI HU
  • Publication number: 20200127559
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Application
    Filed: September 11, 2017
    Publication date: April 23, 2020
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin HU, Yonglu WANG, Zhengping ZHANG, Jian'an WANG, Guangbing CHEN, Dongbing FU, Yuxin WANG, Hequan JIANG, Gangyi HU
  • Patent number: 10003352
    Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: June 19, 2018
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Ting Li, Gangyi Hu, Hequan Jiang, Ruzhang Li, Zhengbo Huang, Yong Zhang, Guangbing Chen, Yuxin Wang, Dongbing Fu
  • Publication number: 20180076824
    Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.
    Type: Application
    Filed: June 8, 2015
    Publication date: March 15, 2018
    Inventors: TING LI, GANGYI HU, HEQUAN JIANG, RUZHANG LI, ZHENGBO HUANG, YONG ZHANG, GUANGBING CHEN, YUXIN WANG, DONGBING FU