Abstract: A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer.

Abstract: A method of forming a metallurgy system on a semiconductor substrate is provided. A first conformal layer of SiO.sub.2 is deposited on the substrate using plasma enhanced chemical vapor deposition (PECVD) techniques. Subsequently a non-conformal organic layer is deposited by spin-on-glass (SOG) techniques over the first layer, and heated to smoothen the surface. The organic SOG deposited layer is then subjected to a N.sub.2 plasma environment and a second conformal layer of SiO.sub.2 is deposited, and then vias etched through the layers. The resist layer used to define vias is removed by an O.sub.2 plasma and the device metallurgy completed.