Abstract: A power-on reset circuit with voltage sensing functions is provided. The invented power-on reset circuit comprises a power voltage sensing circuit and a delay circuit, and an inverter between them. When the supplied power is ON, the power-on reset circuit generates a reset signal. When the voltage of the supplied power is above a predetermined level, the power voltage sensing circuit generates a sensing signal. The sensing signal is input to the delay circuit to generate a delay effect. After a predetermined period of time from the sensing signal, the reset signal is disabled. In addition, when a sudden drop in the supplied power is sensed, a reset signal is generated immediately. Errors in the operation of the circuit may thus be avoided.

Abstract: A comparator circuit used in an analog-to-digital converter includes an input voltage signal line; a reference voltage signal line; a plurality of comparators connected to said input voltage signal line and said reference voltage signal line; a plurality of amplifiers corresponding separately to each of said plurality of comparators and connected respectively between said input voltage signal lines, said reference voltage signal lines, and their corresponding comparators; and a thermocode channel connected to outputs of said plurality of comparators. A plurality of resistors with resistances in a constant ratio are provided in said reference voltage signal line and each is connected between the inputs of two adjacent amplifiers. A plurality of averaging resistors are provided and each is connected between the drains of the input transistor of two adjacent comparators; wherein said plurality of averaging resistors have the same resistance.

Abstract: A comparator circuit used in an analog-to-digital converter includes an input voltage signal line; a reference voltage signal line; a plurality of comparators connected to said input voltage signal line and said reference voltage signal line; a plurality of amplifiers corresponding separately to each of said plurality of comparators and connected respectively between said input voltage signal lines, said reference voltage signal lines, and their corresponding comparators; and a thermocode channel connected to outputs of said plurality of comparators. A plurality of resistors with resistances in a constant ratio are provided in said reference voltage signal line and each is connected between the inputs of two adjacent amplifiers. A plurality of averaging capacitors are provided and each is connected between the outputs of two adjacent comparators; wherein said plurality of averaging capacitors may have the same capacitance.

Abstract: A self-calibrating circuit of a high speed comparator, having a first negative phase logic switch, a second negative logic switch, a first positive phase logic switch, a second positive phase logic switch, a third negative phase logic switch, a fourth negative phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch, a fifth positive phase logic switch, a first current source circuit, a second current source circuit and a control logic circuit. Using the first and the second current source circuits, a self-calibration can be performed while the high speed comparator is just turned on, so that the input offset voltage of the high speed comparator can be eliminated.

Abstract: A voltage-controlled oscillator comprising a voltage compensation transistor is disclosed. The voltage compensation transistor is able to provide an equivalent resistance to the bias voltage supplied to the oscillator. When a sudden raise in the voltage of the power supply takes place, the equivalent resistance of the compensation transistor will drop, such that the bias voltage supplied to the oscillator may be pulled down, whereby the oscillation frequency of the ring oscillator may be adjusted.

Abstract: A pre-charged high-speed comparator includes a first negative phase logic switch, a second negative phase logic switch, a third negative phase logic switch, a first positive phase logic switch, a fourth negative phase logic switch, a second positive phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch and a fifth positive phase logic switch. The two output terminals of the pre-charged high-speed comparator is raised to a voltage roughly half of a source voltage so that the time required for a regeneration circuit that includes the third negative phase logic switch, the first positive phase logic switch, the fourth negative phase logic switch and the second positive phase logic switch to get into the transistor active region is shortened, thereby increasing the overall operating speed of the comparator circuit.