Abstract: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality of photo diode regions and a shielding layer formed overlying the interlayer dielectric layer. A silicon dioxide bearing material is overlying the shielding layer. A plurality of lens structures are formed on the silicon dioxide bearing material. The sensor also has a color filter layer overlying the lens structures and a plurality of second lens structures overlying the color filter layer according to a preferred embodiment.

Abstract: A method for processing a glass substrate is disclosed. A glass substrate including a first surface, a second surface, and a side surface between the first surface and the second surface is provided. An opaque conductive layer is formed on the second surface and a part of the side surface close to the second surface. Thereafter, a semiconductor process is performed on the first surface. Thereafter, the opaque conductive layer on the second surface and the part of the side surface close to the second surface is removed. The problem of transporting a transparent glass substrate by some semiconductor tools is solved without increasing tool cost by enabling the sensing and transportation of glass substrates with optical sensor and/or electrical chuck. The fabrication of devices with a glass substrate is also achieved.

Abstract: A method for fabricating a capacitor includes providing a substrate having a first surface and a second surface, and forming a plurality of openings in the substrate, the openings are separated from each other by a shape of the substrate, each opening having sidewalls and a bottom. The method further includes submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings, and a portion of a surface of the substrate, wherein a shape of the substrate disposed between a pair of two adjacent openings is completely oxidized to form an insulation layer between the pair of two adjacent openings; and depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous and such that the pair of adjacent openings form a capacitor.

Abstract: The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening.

Abstract: An image sensor includes an array of photo-sensing regions formed in a semiconductor substrate, a dielectric layer over the array of photo-sensing regions, and an array of microlenses formed in the dielectric layer. Each of the microlenses is center-aligned over one of the photo-sensing regions and has a truncated plano-convex shape. The microlenses have an index of refraction that is higher than the dielectric layer's refraction index. Each of the microlenses has a smooth circular top, a flat circular bottom, and a curved circumferential side convex towards the semiconductor substrate.

Abstract: An MEMS device and a method for forming the same are provided. The MEMS device comprises a first interlayer dielectric layer on a semiconductor substrate; a cavity in the first interlayer dielectric layer; first openings in the first interlayer dielectric layer over the cavity and connected with the cavity, each first opening comprising a lower portion and an upper portion having non-aligned sidewalls, convex sections are formed in the first interlayer dielectric layer between the lower and upper portions; an electrode being suspended in the cavity and movable relative to the substrate; a second interlayer dielectric layer on the first interlayer dielectric layer; second openings in the second interlayer dielectric layer and connected with the first openings, each second opening is disposed at a location that does not extend past the convex section; a third interlayer dielectric layer fully filling at least the second openings to seal the cavity.

Abstract: A method for fabricating a capacitor includes providing a substrate having a first surface and a second surface, and forming a plurality of openings in the substrate, the openings are separated from each other by a shape of the substrate, each opening having sidewalls and a bottom. The method further includes submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings, and a portion of a surface of the substrate, wherein a shape of the substrate disposed between a pair of two adjacent openings is completely oxidized to form an insulation layer between the pair of two adjacent openings; and depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous and such that the pair of adjacent openings form a capacitor.

Abstract: A method for processing a glass substrate is disclosed. A glass substrate including a first surface, a second surface, and a side surface between the first surface and the second surface is provided. An opaque conductive layer is formed on the second surface and a part of the side surface close to the second surface. Thereafter, a semiconductor process is performed on the first surface. Thereafter, the opaque conductive layer on the second surface and the part of the side surface close to the second surface is removed. The problem of transporting a transparent glass substrate by some semiconductor tools is solved without increasing tool cost by enabling the sensing and transportation of glass substrates with optical sensor and/or electrical chuck. The fabrication of devices with a glass substrate is also achieved.

Abstract: The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening.

Abstract: A method of making an embedded microlens includes providing a substrate having a photo-sensing region, forming a dielectric film overlying the substrate, forming a mask having a circular opening over the dielectric film, the opening being center-aligned over the photo-sensing region, and etching the dielectric film to form a cavity under the mask by introducing an isotropic etchant through the opening, the cavity being characterized by a truncated plano-convex shape having a flat circular bottom and curved peripheral sides convex towards the dielectric film. The method further includes removing the mask, depositing a lens material with a higher refractive index than that of the dielectric film to fill the cavity, planarizing the lens material to form the embedded microlens in the cavity having a smooth top surface, and forming a color filter layer overlying the microlens. The dielectric film includes silicon dioxide having a refractive index of 1.5 or less.

Abstract: Method and structure for electro-plating aluminum species for top metal formation of liquid crystal on silicon displays. In a specific embodiment, the invention provides a method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., semiconductor wafer, silicon wafer, silicon on insulator. The method includes forming a transistor layer (e.g., MOS transistors) overlying the substrate. The method includes forming an interlayer dielectric layer (e.g., PSG, BPSG, FSG) overlying the transistor layer. The method includes forming a first conductive layer overlying the interlayer dielectric layer and forming a second interlayer dielectric layer overlying the first conductive layer. A dual damascene via structure is formed within the second interlayer dielectric layer. The method deposits a barrier metal layer (e.g., TiN, Ti/TiN) within the dual damascene via structure to form a liner that covers exposed regions of the dual damascene via structure.

Abstract: In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer.

Abstract: In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer.

Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.

Abstract: An improved image sensor, e.g., CCD, CID, CMOS. The image sensor includes a substrate, e.g., silicon wafer. The sensor also includes a plurality of photo diode regions, where each of the photo diode regions is spatially disposed on the substrate. The sensor has an interlayer dielectric layer overlying the plurality of photo diode regions and a shielding layer formed overlying the interlayer dielectric layer. A silicon dioxide bearing material is overlying the shielding layer. A plurality of lens structures are formed on the silicon dioxide bearing material. The sensor also has a color filter layer overlying the lens structures and a plurality of second lens structures overlying the color filter layer according to a preferred embodiment.

Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.

Abstract: A method for manufacturing ROM memory devices. The method includes forming a trench isolation structure within a cell region of a semiconductor substrate. The cell region is an array region for ROM memory devices. The method includes forming a gate structure within the cell region and forming a sidewall spacer on the gate structure, which is configured to overlap a portion of the trench isolation structure within the cell region to separate a buried bit line region of the cell region from an adjacent cell region. The method applies a refractory metal layer overlying the gate structure including sidewall spacers and exposed portion of the trench isolation structure. A step of alloying the refractory metal layer to the gate structure and exposed portions of source/drain regions to form silicided regions overlying the gate structure and source/drain regions is included. The refractory metal layer is selectively removed from sidewall spacers and exposed portion of the trench isolation structure.