Abstract: A distributed memory switching hub interconnecting heterogeneous local area networks operating at different transmission speeds for receiving, storing and forwarding frames of data. The distributed memory switching hub employs a distributed memory architecture in which memory storage for frames of data received and to be transmitted is located at each low speed LAN port of the distributed memory switching hub. A distributed memory architecture renders unnecessary the need for a central programmable processor or shared common memory to store and forward frames received by the distributed memory switching hub.

Abstract: A plurality of video dynamic random access memory devices (VRAMs) distributed among low speed local area network ports of a distributed memory switching hub interconnecting heterogeneous local area networks operating at different transmission speeds for receiving, storing and forwarding frames of data. The distributed memory switching hub employs a distributed memory architecture in which VRAM devices located at each low speed LAN port of the distributed memory switching hub store frames of data received or to be forwarded. The VRAM device is comprised of serial access memory (SAM) coupled to and transmitting frames of data with a high speed internal data bus at the same speed of the data bus and dynamic random access memory (RAM) coupled to and transmitting frames of data with a low speed local area network at the same speed of the low speed local area network. The SAM and RAM operate asynchronously with respect to each other to provide simultaneous bidirectional transfer of frames of data between them.

Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.