Abstract: A four stroke internal combustion engine comprising a cylinder block in which is formed a cylinder bore, a piston arranged for reciprocation within the cylinder bore, a cylinder head mounted on the cylinder block and having a conical valve seat embodying inlet and exhaust ports, a conical valve complementary with the valve seat and embodying port hole means via which the inlet or exhaust ports are arranged to communicate with the cylinder bore consequent upon predetermined rotary movement of the valve, and valve rotating means operative to produce at appropriate times during the engine cycle, predetermined rotary movement of the valve in one direction so as to place the inlet port in communication with the cylinder bore via the port hole means or predetermined rotary movement of the valve in the opposite direction so as to place the exhaust port in communication with the cylinder bore via the port hole means.

Abstract: Selective digital signal receiver wherein the time distances between zero crossings of the input voltage are measured with a counter. The zero-crossing counter is preceded by a circuit which, when a zero crossing occurs, is changed to the "on" state, resulting in a counting pulse for the counter, and remains in this state for a dwell time which is only little shorter than the signal-frequency half cycle. Thus, interference pulses can no longer invalidate the counting result of each signal-recognition operation.

Abstract: Selective digital signal receiver wherein the time distances between zero crossings of the input voltage are measured with a counter controlled at a clock frequency which is high compared with the signal frequency. The main check, covering a plurality of cycles and a predetermined bandwith, is always preceded by a pre-check, covering few cycles and a larger bandwidth. This allows early recognition of push-button dial signals.

Abstract: A selective digital signal receiver is disclosed in which the time distances between zero crossings of the input voltages are measured with a counter which is controlled at a clock frequency higher than the signal frequency. Each measurement covers a predetermined number of cycles. The greater the number of cycles chosen, the less the bandwidth must be widened for the zero-crossing shifts caused by noise.