Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. In some embodiments, a memory cell comprises a silicon carbide structure including a charge reservoir configured to store an amount of charge carriers constituting a charge cloud. The amount of charge carriers in the charge cloud can represent a data value. Further, the memory cell includes a resistive element in communication with the charge reservoir and is configured to provide a resistance as a function of the amount of charge carriers in the charge reservoir. The charge reservoir is configured to modulate the size of the charge cloud to change the data value.

Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form barrier structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate, for fabricating various silicon carbide-based semiconductor devices, including silicon carbide-based memory elements and cells. In some embodiments, a semiconductor wafer includes a silicon substrate, a barrier-seed layer disposed over the silicon substrate, and a silicon carbide layer formed over the barrier-seed layer. The semiconductor wafer can be used to form a variety of SiC-based semiconductor devices. In one embodiment, a silicon carbide-based memory element is formed to include barrier-seed layer, multiple silicon carbide layers formed over the barrier-seed layer, and a dielectric layer formed over the multiple silicon carbide layers.

Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form film structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate. In some embodiments, a method of preparing a substrate for silicon carbide epitaxial layer formation can include forming an ultrathin layer of oxide that is configured to inhibit contaminants from interacting with a silicon-based substrate. Further, the method can include forming a carbonized film on the silicon-based substrate that is configured to inhibit contaminants from interacting with the silicon-based substrate. The carbonized film can be configured to be transitory as fabrication parameters are modified to form an epitaxial layer of silicon carbide.

Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant.

Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. In some embodiments, a memory cell comprises a silicon carbide structure including a charge reservoir configured to store an amount of charge carriers constituting a charge cloud. The amount of charge carriers in the charge cloud can represent a data value. Further, the memory cell includes a resistive element in communication with the charge reservoir and is configured to provide a resistance as a function of the amount of charge carriers in the charge reservoir. The charge reservoir is configured to modulate the size of the charge cloud to change the data value.