Abstract: An apparatus comprises touch screen interface and signal processing circuit. Within touch screen interface, there are switching circuits configured to be coupled to at least one of a plurality of column electrodes, and there are touch detection circuits configured to be coupled to at least one of a plurality of row electrodes. The signal processing circuit is coupled to each switching circuit and each touch detection circuit so as to be able to selectively activate the plurality of switching circuits and touch detection circuits to identify a zone for a touch event. The signal processing circuit determines first, second, third, and fourth resistances for the zone for the touch event and determines a set of coordinates and pressure for the touch event from its first, second, third, and fourth resistances wherein an aperture filter register is in a host interface that also stores the first digital representation.

Abstract: An apparatus comprises touch screen interface and signal processing circuit. Within touch screen interface, there are switching circuits configured to be coupled to at least one of a plurality of column electrodes, and there are touch detection circuits configured to be coupled to at least one of a plurality of row electrodes. The signal processing circuit is coupled to each switching circuit and each touch detection circuit so as to be able to selectively activate the plurality of switching circuits and touch detection circuits to identify a zone for a touch event. The signal processing circuit determines first, second, third, and fourth resistances for the zone for the touch event and determines a set of coordinates and pressure for the touch event from its first, second, third, and fourth resistances wherein an aperture filter register is in a host interface that also stores the first digital representation.

Abstract: An apparatus comprises touch screen interface and signal processing circuit. Within touch screen interface, there are switching circuits configured to be coupled to at least one of a plurality of column electrodes, and there are touch detection circuits configured to be coupled to at least one of a plurality of row electrodes. The signal processing circuit is coupled to each switching circuit and each touch detection circuit so as to be able to selectively activate the plurality of switching circuits and touch detection circuits to identify a zone for a touch event. The signal processing circuit determines first, second, third, and fourth resistances for the zone for the touch event and determines a set of coordinates and pressure for the touch event from its first, second, third, and fourth resistances wherein an aperture filter register is in a host interface that also stores the first digital representation.

Abstract: An apparatus is provided. The apparatus comprises a touch screen interface and a signal processing circuit. Within the touch screen interface, there are switching circuits, where each switching circuit is configured to be coupled to a column electrode, and there are touch detection circuits, where each touch detection circuit is configured to be coupled to a row electrode. The signal processing circuit is then coupled to each switching circuit and each touch detection circuit so as to be able to selectively activate the plurality of switching circuits and the plurality of touch detection circuits to identify a zone for a touch event. Also, the signal processing circuit is configured to determine first, second, third, and fourth resistances for the zone for the touch event and is configured to determine a set of coordinates and pressure for the touch event from its first, second, third, and fourth resistances.

Abstract: Internal servo loop circuitry is included on the same chip (10C) with an ADC (10B). Automatic test equipment (12) operates with the internal servo loop circuitry and external servo loop circuitry (1B) to test the ADC. The internal servo loop circuitry includes a target register (14), a digital comparator (18), and a crossover counter (22). An integrator (32) responsive to the digital comparator (18) produces an input signal (Vin) to the ADC, which generates a corresponding digital output sample (Dout). The comparator compares the output sample with a target code in the target register and causes the direction of the input signal to reverse each time the digital output sample crosses over the target code. The counter causes a voltmeter to measure a transition voltage value of the input voltage after a predetermined number of crossovers.

Abstract: A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.

Abstract: The traditional method of scan insertion and balancing clocks involves first having a system clock, which can be used for scan mode and normal mode, then synthesizing the design, defining scan chain or scan chains, and inserting them in the design using a script. After that, the cells are placed in a layout and the clock trees are balanced. In accordance with the present invention, however, prior to synthesis, dummy elements are added to the library and an internal scan clock pin with no connections is provided. Then the design is synthesized, scan insertion is performed (defining scan chains, inserting chains), and the scan clock is connected to all flip-flops SCLK pins. Finally, the dummy elements are replaced with real gates and clock tree insertion is performed after placing the cell in a layout.

Abstract: A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.