Abstract: A hierarchical configurable gate array is disclosed and includes a plurality of cluster regions (10,20,30,40) arranged in different levels. The first level cluster (10) includes an integral number N multi-terminal components for providing canonical functions. The second level cluster (20) includes N first level clusters; and higher level clusters (30,40) each includes N clusters of the next lower level. Interconnect regions (13,15,17,19) are provided within each cluster for interconnections between the N elements of each level. Selected input or output ports for each element of a cluster are available for interconnection at more than one location.