Patents by Inventor Herbert Gietler

Herbert Gietler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10381919
    Abstract: A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies AG
    Inventors: Albino Pidutti, Damiano Gadler, Herbert Gietler, Michael Lenz, Yavuz Kilic, Ioannis Pachnis
  • Patent number: 10291108
    Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: May 14, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Frank Auer, Herbert Gietler, Michael Lenz
  • Publication number: 20180167000
    Abstract: A rectifier device is described herein. In accordance with one example, the rectifier device includes a transistor that has a load current path and a diode connected parallel to the load current path. The diode and the load current path are connected between an anode terminal and a cathode terminal; an alternating input voltage is operably applied between the anode terminal and the cathode terminal. A control circuit is coupled to a gate terminal of the transistor and configured to switch the semiconductor switch on for an on-time period, during which the diode is forward biased. Moreover, a clamping circuit is coupled to a gate terminal of the transistor and configured to at least partly switch on the transistor, while the diode is reverse biased and the level of the alternating input voltage reaches a clamping voltage.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Albino Pidutti, Damiano Gadler, Herbert Gietler, Michael Lenz
  • Publication number: 20180166971
    Abstract: A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Albino Pidutti, Damiano Gadler, Herbert Gietler, Michael Lenz, Yavuz Kilic, Ioannis Pachnis
  • Patent number: 9997608
    Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Karoline Koepp, Herbert Gietler
  • Publication number: 20170257037
    Abstract: A power semiconductor package includes a reference voltage terminal, a supply voltage terminal, a phase terminal, a first power transistor and a second power transistor. The first power transistor and the second power transistor are connected in series and form a low side switch and a high side switch of a half bridge circuit.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 7, 2017
    Applicant: Infineon Technologies AG
    Inventors: Juergen Kositza, Herbert Gietler, Harald Huber, Michael Lenz
  • Patent number: 9728480
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Publication number: 20170200795
    Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 13, 2017
    Inventors: Karoline Koepp, Herbert Gietler
  • Publication number: 20170133289
    Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Inventors: Herbert Gietler, Robert Pressl
  • Patent number: 9589914
    Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: March 7, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Herbert Gietler, Robert Pressl
  • Publication number: 20160155712
    Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.
    Type: Application
    Filed: November 28, 2014
    Publication date: June 2, 2016
    Inventors: Herbert Gietler, Robert Pressl
  • Publication number: 20160072376
    Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.
    Type: Application
    Filed: September 10, 2015
    Publication date: March 10, 2016
    Inventors: Dirk Ahlers, Frank Auer, Herbert Gietler, Michael Lenz
  • Publication number: 20150235917
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 8766444
    Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: July 1, 2014
    Assignee: Infineon Technologies AG
    Inventors: Herbert Gietler, Gerhard Zojer, Benjamin Finke
  • Patent number: 8737034
    Abstract: A method determines a change in the activation state of an electromagnetic actuator.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Herbert Gietler, Heinz Zitta
  • Publication number: 20140117511
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Patent number: 8643990
    Abstract: A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Yiqun Cao, Herbert Gietler, Ulrich Glaser
  • Patent number: 8378491
    Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: February 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Herbert Gietler, Gerhard Zojer, Benjamin Finke
  • Publication number: 20120049373
    Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.
    Type: Application
    Filed: August 24, 2010
    Publication date: March 1, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Herbert Gietler, Gerhard Zojer, Benjamin Finke
  • Publication number: 20110304940
    Abstract: A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal.
    Type: Application
    Filed: May 20, 2011
    Publication date: December 15, 2011
    Applicant: Infineon Technologies AG
    Inventors: Yiqun Cao, Herbert Gietler, Ulrich Glaser