Patents by Inventor Herbert Gietler
Herbert Gietler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10522432Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.Type: GrantFiled: January 24, 2017Date of Patent: December 31, 2019Assignee: Infineon Technologies AGInventors: Herbert Gietler, Robert Pressl
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Patent number: 10516343Abstract: A power semiconductor package includes a reference voltage terminal, a supply voltage terminal, a phase terminal, a first power transistor and a second power transistor. The first power transistor and the second power transistor are connected in series and form a low side switch and a high side switch of a half bridge circuit.Type: GrantFiled: March 1, 2017Date of Patent: December 24, 2019Assignee: Infineon Technologies AGInventors: Juergen Kositza, Herbert Gietler, Harald Huber, Michael Lenz
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Patent number: 10381919Abstract: A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.Type: GrantFiled: December 14, 2016Date of Patent: August 13, 2019Assignee: Infineon Technologies AGInventors: Albino Pidutti, Damiano Gadler, Herbert Gietler, Michael Lenz, Yavuz Kilic, Ioannis Pachnis
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Patent number: 10291108Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.Type: GrantFiled: September 10, 2015Date of Patent: May 14, 2019Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Frank Auer, Herbert Gietler, Michael Lenz
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Publication number: 20180167000Abstract: A rectifier device is described herein. In accordance with one example, the rectifier device includes a transistor that has a load current path and a diode connected parallel to the load current path. The diode and the load current path are connected between an anode terminal and a cathode terminal; an alternating input voltage is operably applied between the anode terminal and the cathode terminal. A control circuit is coupled to a gate terminal of the transistor and configured to switch the semiconductor switch on for an on-time period, during which the diode is forward biased. Moreover, a clamping circuit is coupled to a gate terminal of the transistor and configured to at least partly switch on the transistor, while the diode is reverse biased and the level of the alternating input voltage reaches a clamping voltage.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventors: Albino Pidutti, Damiano Gadler, Herbert Gietler, Michael Lenz
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Publication number: 20180166971Abstract: A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventors: Albino Pidutti, Damiano Gadler, Herbert Gietler, Michael Lenz, Yavuz Kilic, Ioannis Pachnis
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Patent number: 9997608Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.Type: GrantFiled: January 12, 2017Date of Patent: June 12, 2018Assignee: Infineon Technologies AGInventors: Karoline Koepp, Herbert Gietler
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Publication number: 20170257037Abstract: A power semiconductor package includes a reference voltage terminal, a supply voltage terminal, a phase terminal, a first power transistor and a second power transistor. The first power transistor and the second power transistor are connected in series and form a low side switch and a high side switch of a half bridge circuit.Type: ApplicationFiled: March 1, 2017Publication date: September 7, 2017Applicant: Infineon Technologies AGInventors: Juergen Kositza, Herbert Gietler, Harald Huber, Michael Lenz
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Patent number: 9728480Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.Type: GrantFiled: April 29, 2015Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
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Publication number: 20170200795Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.Type: ApplicationFiled: January 12, 2017Publication date: July 13, 2017Inventors: Karoline Koepp, Herbert Gietler
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Publication number: 20170133289Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Inventors: Herbert Gietler, Robert Pressl
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Patent number: 9589914Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.Type: GrantFiled: November 28, 2014Date of Patent: March 7, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Herbert Gietler, Robert Pressl
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Publication number: 20160155712Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.Type: ApplicationFiled: November 28, 2014Publication date: June 2, 2016Inventors: Herbert Gietler, Robert Pressl
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Publication number: 20160072376Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.Type: ApplicationFiled: September 10, 2015Publication date: March 10, 2016Inventors: Dirk Ahlers, Frank Auer, Herbert Gietler, Michael Lenz
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Publication number: 20150235917Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.Type: ApplicationFiled: April 29, 2015Publication date: August 20, 2015Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Silvana Fister, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
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Patent number: 8766444Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.Type: GrantFiled: January 11, 2013Date of Patent: July 1, 2014Assignee: Infineon Technologies AGInventors: Herbert Gietler, Gerhard Zojer, Benjamin Finke
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Patent number: 8737034Abstract: A method determines a change in the activation state of an electromagnetic actuator.Type: GrantFiled: January 13, 2010Date of Patent: May 27, 2014Assignee: Infineon Technologies AGInventors: Herbert Gietler, Heinz Zitta
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Publication number: 20140117511Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: Infineon Technologies AGInventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
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Patent number: 8643990Abstract: A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal.Type: GrantFiled: May 20, 2011Date of Patent: February 4, 2014Assignee: Infineon Technologies AGInventors: Yiqun Cao, Herbert Gietler, Ulrich Glaser
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Patent number: 8378491Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.Type: GrantFiled: August 24, 2010Date of Patent: February 19, 2013Assignee: Infineon Technologies AGInventors: Herbert Gietler, Gerhard Zojer, Benjamin Finke