Abstract: A switch controller for a dynamic switch responds to command from a using system to provide control signals to the dynamic switch which causes the switch to establish and breakdown paths between sources and destinations in the using system. The controller includes a plurality of command registers which are temporarily assigned to a command source for receiving command signals, decoding said signals and providing control signals to the switch for establishing or breaking down a switch path. The controller may if desired provide an echo to a selected destination so that proper execution of commands may be ascertained. After the commands are completed the control register is released for reassignment to another command source while an established switch path remains intact. Thus, commands may be received from any source for controlling the switch.

Abstract: An interface for effecting the direct transfer of message segments between an intelligent switch and a microcomputer includes an input buffer, an output buffer and a memory for storing address to be associated with the message segments traversing the buffers.

Abstract: An interface for use with a microcomputer is provided with memory that in one operating mode is used as a first-in first-out buffer, and in a second operating mode allows the direct data transfer across the interface. The interface also includes a means for selecting the operating mode thereof.

Abstract: A CAM/RAM/CAM memory array is used to provide dynamic space and time switching between a plurality of sources and destinations. The memory array includes a source CAM portion, a destination CAM portion and a data RAM portion with each row forming a word. In order to establish a path, a source address is stored in the source CAM portion of a word and a destination address is stored in the destination CAM portion of the same word. When data is to be switched, the data source address is presented to the source CAM on a TDM address bus to address a word having the same source address. The data is then written into the RAM of the addressed word from a data bus, if an address comparison is found. The address of the destination is time division multiplexed to the destination CAM via a destination address bus. If the address of the data destination on the address bus matches a stored address, the data RAM associated with the address is enabled and read to the data bus for delivery to the data destination.

Abstract: An apparatus for establishing a plurality of communication paths includes a plurality of ports each having different data rates associated therewith and a means for establishing simultaneous paths among the plurality of ports according to instruction signals from terminals interfaced with the ports and carried on the same path as the information to be switched.

Abstract: A system is disclosed which permits information received from any data terminal or telephone subscriber line at any interface to a digital network to be transmitted to any number of other terminals at any or all of the interfaces to the digital network. The system herein described also permits any terminal at any interface of the digital network to be conferenced, with up to N other terminals at any or all of the interfaces to the digital network where N can be made to depend solely upon the topology and single path transmission delay of the digital network itself. A facility is provided which is independently provisioned at every interface to the digital network and which is independently and concurrently available to any number of combinations of terminals and simplex paths at those interfaces. A broadcast capability is also provided whereby telecommunication information can be simultaneously transmitted from a source terminal to a plurality of destination terminals.