Abstract: A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

Abstract: The disclosure provides an oscillator circuit for a voltage controlled oscillator. The oscillator circuit includes first and second coupled transmission lines, wherein the oscillator circuit is configured to provide a variable load impedance at a first end of a signal line of the first transmission line such that a variable inductance is provided between first and second ends of a signal line of the second transmission line in dependence on the variable load impedance. The oscillator circuit is configured to adjust the variable inductance provided between the first and second ends of the signal line of the second transmission line by adjusting the variable load impedance provided at the first end of the signal line of the first transmission line, wherein the variable inductance provided between the first and second ends of the signal line of the second transmission line constitutes a frequency determining element of the oscillator circuit.

Abstract: A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip.

Abstract: The present invention relates to a millimeter-wave transmitter on a chip comprising at least one transmit path coupleable to an oscillator, and an on-chip power sensor to measure at least a portion of a transmit power transmitted over the at least one transmit path. The present invention further relates to a method of calibrating a millimeter-wave transmitter on a chip and an on-chip power sensor coupleable to at least one transmit path of a millimeter-wave transmitter. The embodiments of the present invention provide a direct measure of transmit power provided within an individual one of the transmit paths of the millimeter-wave transmitter.

Abstract: A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

Abstract: A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

Abstract: A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

Abstract: A DC power supply circuit comprises an output configured to provide a power supply signal to an RF element for generating an RF output signal. Furthermore, the DC power supply circuit comprises an input configured to receive the RF output signal. The DC power supply circuit is configured to generate the DC power supply signal based on the received RF output signal.

Abstract: A DC power supply circuit comprises an output configured to provide a power supply signal to an RF element for generating an RF output signal. Furthermore, the DC power supply circuit comprises an input configured to receive the RF output signal. The DC power supply circuit is configured to generate the DC power supply signal based on the received RF output signal.

Abstract: Embodiments relate to apparatuses, systems and methods for testing high-frequency receivers. In an embodiment, a method includes integrating a pulse train generator and a receiver in an integrated circuit; generating a pulse train by the pulse train generator and applying the pulse train to an input of the receiver; measuring at least one property of the pulse train; and determining at least one characteristic of the receiver using the at least one property of the pulse train. In an embodiment, an integrated circuit includes a receiver, and a pulse train generator configured to generate a pulse train and apply the pulse train to an input of the receiver, wherein at least one characteristic of the receiver can be determined using at least one measured property of the pulse train.

Abstract: A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip.

Abstract: A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: Embodiments relate to apparatuses, systems and methods for testing high-frequency receivers. In an embodiment, a method includes integrating a pulse train generator and a receiver in an integrated circuit; generating a pulse train by the pulse train generator and applying the pulse train to an input of the receiver; measuring at least one property of the pulse train; and determining at least one characteristic of the receiver using the at least one property of the pulse train. In an embodiment, an integrated circuit includes a receiver, and a pulse train generator configured to generate a pulse train and apply the pulse train to an input of the receiver, wherein at least one characteristic of the receiver can be determined using at least one measured property of the pulse train.

Abstract: A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.

Abstract: One embodiment relates to a frequency divider. The frequency divider includes an active mixer having a first mixer input, a second mixer input, and a mixer output. The first mixer input is adapted to receive an input signal having an input frequency, and the mixer output is adapted to provide a mixed signal based on the input signal. The frequency divider also includes an amplification element having an amplification input and an amplification output. The amplification input is adapted to receive the mixed signal and the amplification output is adapted to provide an amplification output signal having an output frequency. A feedback path, which includes an alternating current (AC) coupling element, couples the amplification output to the second mixer input. Other systems and methods are also disclosed.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes an output circuit having at least one first output connection which can provide a data signal, at least one first data output connection; and at least one first inductance connected between the at least one first output connection and the at least one data output connection.

Abstract: An ESD protection circuit is disclosed. In one embodiment, the ESD circuit is coupled to at least one signal transmission line and a positive and negative supply voltage of an integrated circuit, and includes at least one ESD-element connected between the signal transmission line and either one of the positive or negative supply voltages. At least one high-frequency transmission line is connected in series to the ESD-element and dimensioned in such a way that, at a predetermined high-frequency of a signal, an impedance of the current-path via the ESD-element is transformed, compared with the system impedance, from a low impedance to a very high impedance.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: An ESD protection circuit is disclosed. In one embodiment, the ESD circuit is coupled to at least one signal transmission line and a positive and negative supply voltage of an integrated circuit, and includes at least one ESD-element connected between the signal transmission line and either one of the positive or negative supply voltages. At least one high-frequency transmission line is connected in series to the ESD-element and dimensioned in such a way that, at a predetermined high-frequency of a signal, an impedance of the current-path via the ESD-element is transformed, compared with the system impedance, from a low impedance to a very high impedance.