Abstract: A method and apparatus for generating a phase-locked output signal includes generating an intermediate signal phase locked to an input signal by frequency dividing the intermediate signal by a temporally-varying divide ratio sequence to generate a first feedback signal and phase comparing the first feedback signal with the input signal. An output signal is generated phase locked to the first feedback signal by frequency dividing the output signal by the temporally-varying divide ratio sequence to generate a second feedback signal and phase comparing the second feedback signal with the first feedback signal.

Abstract: A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.

Abstract: A SQUID comparator having two junctions configured so that its operating characteristics are substantially the same as a single junction SQUID. In particular, the ratio of the critical current of these two junctions is selected to avoid introduction of hysteresis. An n-bit single pass comparator is present that can produce 4-bit A/D conversion up to 10 GHz. A method is implemented to remove effects of dynamic hysteresis by use complementary comparators.