Abstract: A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

Abstract: A shifter circuit comprises, in one embodiment, an input voltage divider stage comprising multiple transistors arranged in a transistor stack defining a plurality of intermediate nodes. The transistor stack is connected between an input signal and ground and has at least one output. An inverting buffer stage is connected to a supply voltage and coupled to the input voltage divider's output. The inverting buffer stage is configured to provide an inverted output signal. Means are provided for stepping up the inverted output signal, receiving a stepped up output signal and providing a level-shifted output signal at a voltage level lower than that of the input signal.

Abstract: Shifter circuits comprise a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors. The matched translation stack is configured to provide a primary logic level shift between a voltage level away from which a shift is desired (VddL) and a voltage level to which the shift is desired (VddH). One or more high voltage buffer stages are provided, at least one of which being connected with and biased by the matched translation stack. At least one high voltage buffer stage comprises multiple transistors arranged in a transistor stack that is biased by the first stack of the matched translation stack, and is connected to receive an input supplied by the second stack of the matched translation stack. The high voltage buffer stage also comprises an inverter that drives an output stage which is also driven by a low voltage buffer stage.

Abstract: A power conversion system for driving a three phase synchronous or induction motor receives power from AC power lines and rectifies the power to provide DC current on DC link lines through a link inductor. An inverter connected to the DC link lines is composed of three sets of two thyristors connected in series across the DC link lines. Three output lines extend from connections between each of the three sets of thyristors to the motor. Capacitors are connected across each of the three phase output lines. A controller controls the switching of the thyristors in two modes. In a first mode, used from start-up to low speed operation, a high frequency switching cycle is produced in three steps during which pairs of thyristors in different ones of the three sets are triggered. The relative length of time spent in each one of the three periods during the switching cycle is varied to obtain a desired change in the average output voltage on the three phase output lines at a fundamental frequency.