Abstract: There is provided a phase-locked loop clock circuit being operable in a tracking mode in response to a reference signal and in a sustaining mode in the absence of a reference signal. The circuit provides a relatively stable output clock signal in either of the two modes and permits smooth switchovers from one reference signal to another in a system with multiple reference signals. The circuit further provides a stable output clock if a reference signal temporarily fails.

Abstract: In a merchandising business wherein telephone subscribers' responses are solicited by various commercial advertisements via the television and/or radio media, merchandising agents receive such telephone responses in order to accept requests for goods and services and to expedite deliveries and billings. A telephone system is disclosed wherein a portion of a direct dialled number associated with an advertised product is forwarded to an information server. The information server provides information about the product, such information being displayable at a data display terminal adjacent a merchandising agent's position. In the case where a group of merchandising agents is accessed via an automatic call distributing feature in the telephone system, the voice call and the data information appear at a selected merchandising agent's position at about the same time, thereby informing the agent as to the particular item of interest and its attributes in association with the voice call.

Abstract: The conversion of bit-interleaved to byte-interleaved data is achieved using a memory and a universal shift register. The period of each bit-interleaved timeslot is divided into three parts for which corresponding timing signals are provided. During the first timing signal, the content of a memory location corresponding to an output channel is loaded into the universal shift register. During the second timing signal, the incoming bit associated with the timeslot is shifted serially into the register and during the third signal, the content of the register is returned to its original location in memory. After a frame of bit-interleaved data has been received at the register, the memory contains the corresponding frame of byte-interleaved data.