Patents by Inventor Herbert Lei Ho
Herbert Lei Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9171848Abstract: An integrated circuit structure provides at least one metal-insulator-metal (MIM) capacitor and a moat isolation structure wherein the number of processes required is substantially minimized and the formation of the MIM capacitor and the moat isolation structure effectively decouple while the number of processes common to the moat isolation structure and the MIM capacitor are maximized. Additional required processes are non-critical and tolerant of overlay positioning error.Type: GrantFiled: November 22, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Thomas Walter Dyer, Herbert Lei Ho, Jin Liu
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Patent number: 9059194Abstract: Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. Control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.Type: GrantFiled: January 10, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Colin J. Brodsky, Anne C. Friedman, Herbert Lei Ho, Byeong Yeol Kim, Dan Mihai Mocuta, Garrett W. Oakley, Chienfan Yu
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Publication number: 20150145102Abstract: An integrated circuit structure provides at least one metal-insulator-metal (MIM) capacitor and a moat isolation structure wherein the number of processes required is substantially minimized and the formation of the MIM capacitor and the moat isolation structure effectively decouple while the number of processes common to the moat isolation structure and the MIM capacitor are maximized. Additional required processes are non-critical and tolerant of overlay positioning error.Type: ApplicationFiled: November 22, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: Thomas Walter Dyer, Herbert Lei Ho, Jin Liu
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Publication number: 20150102463Abstract: Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.Type: ApplicationFiled: December 22, 2014Publication date: April 16, 2015Inventors: Colin J. Brodsky, Anne C. Friedman, Herbert Lei Ho, Byeong Yeol Kim, Dan Mihai Mocuta, Garrett W. Oakley, Chienfan Yu
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Publication number: 20140191366Abstract: Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Colin J. Brodsky, Anne C. Friedman, Herbert Lei Ho, Byeong Yeol Kim, Dan Mihai Mocuta, Garrett W. Oakley, Chienfan Yu
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Patent number: 8642440Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.Type: GrantFiled: October 24, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Chengwen Pei, Roger Allen Booth, Jr., Herbert Lei Ho, Naoyoshi Kusaba
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Publication number: 20130099354Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.Type: ApplicationFiled: October 24, 2011Publication date: April 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chengwen Pei, Roger Allen Booth, JR., Herbert Lei Ho, Naoyoshi Kusaba
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Patent number: 8343864Abstract: A semiconductor circuit and method of fabrication is disclosed. In one embodiment, the semiconductor circuit comprises a metal-insulator-metal trench capacitor in a silicon substrate. A field effect transistor is disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor, and a silicide region is disposed between the field effect transistor and the metal-insulator-metal trench capacitor. Electrical connectivity between the transistor and capacitor is achieved without the need for a buried strap.Type: GrantFiled: March 28, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Puneet Goyal, Herbert Lei Ho, Pradeep Jana, Jin Liu
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Publication number: 20120248522Abstract: A semiconductor circuit and method of fabrication is disclosed. In one embodiment, the semiconductor circuit comprises a metal-insulator-metal trench capacitor in a silicon substrate. A field effect transistor is disposed on the silicon substrate adjacent to the metal-insulator-metal trench capacitor, and a silicide region is disposed between the field effect transistor and the metal-insulator-metal trench capacitor. Electrical connectivity between the transistor and capacitor is achieved without the need for a buried strap.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Puneet Goyal, Herbert Lei Ho, Pradeep Jana, Jin Liu
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Patent number: 8159040Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.Type: GrantFiled: May 13, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert Lei Ho, Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping-Chuan Wang, Hongwen Yan
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Patent number: 7682896Abstract: The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material. The semiconductor device contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region.Type: GrantFiled: May 18, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, Subramanian Srikanteswara Iyer, Vidhya Ramachandran
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Publication number: 20090283840Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.Type: ApplicationFiled: May 13, 2008Publication date: November 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert Lei Ho, Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping-Chuan Wang, Hongwen Yan
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Patent number: 7564086Abstract: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.Type: GrantFiled: December 4, 2006Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Kim Bosang, Herbert Lei Ho, Ali Babar Khan, Deok-kee Kim
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Patent number: 7491994Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.Type: GrantFiled: August 31, 2005Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Herbert Lei Ho, Louis Lu-Chen Hsu, Jack Allan Mandelman
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Patent number: 7153737Abstract: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.Type: GrantFiled: January 17, 2005Date of Patent: December 26, 2006Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Kim Bosang, Herbert Lei Ho, Babar Ali Khan, Deok-kee Kim
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Patent number: 6553561Abstract: A method for generating a patterned SOI photomask used for embedded DRAMs is described. The method systematically identifies embedded DRAM areas to be excluded from the SOI process and generates the shapes to be printed on the photomask so that the embedded DRAM may be fabricated on bulk silicon. The method includes the steps of: identifying and sorting DRAM array well shapes by common electrical net, resulting in a single array well shape for each electrical net (i.e., embedded DRAM cell). Next, all the n-band contacts touching a given array well shape are collected. These shapes are merged by common electrical net. A shape is then generated which is the smallest enclosing rectangle of the common electrical net of the n-band contact shapes. This represents the patterned SOI shape and defines the bulk areas onto which the embedded DRAM is to be built. Accordingly, the embedded DRAM macro is constructed in bulk areas while the logic is constructed in SOI.Type: GrantFiled: August 2, 2001Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Karen Ann Bard, Herbert Lei Ho
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Publication number: 20030028855Abstract: A method for generating a patterned SOI photomask used for embedded DRAMs is described. The method systematically identifies embedded DRAM areas to be excluded from the SOI process and generates the shapes to be printed on the photomask so that the embedded DRAM may be fabricated on bulk silicon. The method includes the steps of: identifying and sorting DRAM array well shapes by common electrical net, resulting in a single array well shape for each electrical net (i.e., embedded DRAM cell). Next, all the n-band contacts touching a given array well shape are collected. These shapes are merged by common electrical net. A shape is then generated which is the smallest enclosing rectangle of the common electrical net of the n-band contact shapes. This represents the patterned SOI shape and defines the bulk areas onto which the embedded DRAM is to be built. Accordingly, the embedded DRAM macro is constructed in bulk areas while the logic is constructed in SOI.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventors: Karen Ann Bard, Herbert Lei Ho
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Patent number: 6153474Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.Type: GrantFiled: July 1, 1998Date of Patent: November 28, 2000Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, Radhika Srinivasan, Scott D. Halle, Erwin Hammerl, David M. Dobuzinsky, Jack Allan Mandelman, Mark Anthony Jaso
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Patent number: 6015985Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.Type: GrantFiled: June 17, 1997Date of Patent: January 18, 2000Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, David Edward Kotecki, Carl John Radens
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Patent number: 6014310Abstract: A composite dielectric material useful in advanced memory applications such as dynamic random access memory (DRAM) cells is provided. The composite dielectric material of the present invention includes a mixed oxide such as TiO.sub.2 or Ta.sub.2 O.sub.5 that is interdiffused into a Si.sub.3 N.sub.4 film. Capacitors including the composite dielectric material of the present invention are also disclosed.Type: GrantFiled: October 21, 1998Date of Patent: January 11, 2000Assignee: International Business Machines CorporationInventors: Gary Bela Bronner, Stephan Alan Cohen, David Mark Dobuzinsky, Jeffrey Peter Gambino, Herbert Lei Ho, Karen Popek Madden