Patents by Inventor Herbert Schafer
Herbert Schafer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8178966Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.Type: GrantFiled: November 5, 2010Date of Patent: May 15, 2012Assignee: Infineon Technologies AGInventors: Volker Lehmann, Reinhard Stengl, Herbert Schäfer
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Publication number: 20120074405Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: ApplicationFiled: December 8, 2011Publication date: March 29, 2012Applicant: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Publication number: 20120023478Abstract: A method replaces a controller, particularly a faulty and/or outmoded controller, in an onboard power supply system in a vehicle. The controller to be replaced is replaced by a functional and/or new controller. The controller to be replaced and the new controller are operated by incompatible operating software. In the method at least one software component is exported from a software development environment for the operating software of the controller to be replaced by a data processing apparatus. The software component is converted into a code, which can be imported into a software development environment for the operating software of the functional and/or new controller, by the data processing apparatus. The code is imported into the software development environment of the operating software of the functional and/or new controller by the data processing apparatus. The operating software for the new controller is produced on the basis of the imported code.Type: ApplicationFiled: July 25, 2011Publication date: January 26, 2012Applicant: MAN TRUCK & BUS AGInventors: Herbert Schäfer, Marc Witte
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Patent number: 8102052Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: GrantFiled: February 14, 2011Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 8003475Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.Type: GrantFiled: March 20, 2008Date of Patent: August 23, 2011Assignee: Infineon Technologies AGInventors: Josef Böck, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schäfer, Martin Seck
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Patent number: 7968972Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.Type: GrantFiled: March 3, 2010Date of Patent: June 28, 2011Assignee: Infineon Technologies AGInventors: Josef Böck, Thomas Meister, Reinhard Stengl, Herbert Schäfer
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Publication number: 20110133188Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 7947552Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: GrantFiled: April 21, 2008Date of Patent: May 24, 2011Assignee: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Publication number: 20110042046Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.Type: ApplicationFiled: November 5, 2010Publication date: February 24, 2011Inventors: Volker Lehmann, Reinhard Stengl, Herbert Schäfer
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Publication number: 20100155896Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Inventors: Josef Böck, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7719088Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.Type: GrantFiled: October 20, 2005Date of Patent: May 18, 2010Assignee: Infineon Technologies AGInventors: Josef Böck, Thomas Meister, Reinhard Stengl, Herbert Schäfer
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Patent number: 7612430Abstract: The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).Type: GrantFiled: June 15, 2001Date of Patent: November 3, 2009Assignee: Infineon Technologies AGInventors: Martin Franosch, Thomas Meister, Herbert Schäfer, Reinhard Stengl, Konrad Wolf
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Patent number: 7459365Abstract: The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.Type: GrantFiled: September 29, 2006Date of Patent: December 2, 2008Assignee: Infineon Technologies Austria AGInventors: Michael Rüb, Herbert Schäfer, Armin Willmeroth, Anton Mauder, Stefan Sedlmaier, Roland Rupp, Manfred Pippan, Hans Weber, Frank Pfirsch, Franz Hirler, Hans-Joachim Schulze
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Patent number: 7449389Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.Type: GrantFiled: October 27, 2006Date of Patent: November 11, 2008Assignee: Infineon Technologies AGInventors: Thomas Meister, Herbert Schäfer, Josef Böck, Rudolf Lachner
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Publication number: 20080227261Abstract: The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths. The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages.Type: ApplicationFiled: March 20, 2008Publication date: September 18, 2008Inventors: Josef Bock, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schafer, Martin Seck
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Patent number: 7420228Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.Type: GrantFiled: October 7, 2005Date of Patent: September 2, 2008Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7371650Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.Type: GrantFiled: October 24, 2003Date of Patent: May 13, 2008Assignee: Infineon Technologies AGInventors: Josef Böck, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schäfer, Martin Seck
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Publication number: 20080102593Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.Type: ApplicationFiled: October 27, 2006Publication date: May 1, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas Meister, Herbert Schafer, Josef Bock, Rudolf Lachner
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Patent number: 7285470Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component.Type: GrantFiled: September 30, 2005Date of Patent: October 23, 2007Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Reinhard Stengl, Herbert Schafer
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Patent number: 7256472Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.Type: GrantFiled: July 11, 2003Date of Patent: August 14, 2007Assignee: Infineon Technologies AGInventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schäfer