Abstract: A high-speed, low-latency configurable digital interface for a voltage regulator includes a first hardwired unit, a second hardwired unit and a programmable microcontroller interfaced between the first and second hardwired units. The first hardwired unit is operable to deserialize incoming frames received over the configurable digital interface into commands and data associated with operation of a switching voltage regulator, and serialize outgoing data into new frames for transmission over the configurable digital interface. The second hardwired unit is operable to process the commands included in the incoming frames deserialized by the first hardwired unit, and provide the outgoing data to be serialized into new frames by the first hardwired unit. The programmable microcontroller is operable to change one or more of the commands and data flowing between the first and second hardwired units.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate that one or more of the power stages is faulty and disabled; communicate the throttling signal to the processor over a physical line running between the processor and the controller; and place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: A multiphase voltage regulator includes a plurality of power stages, a plurality of current sense circuits, a controller and a current sense interface running between the controller and one or more of the current sense circuits. The current sense interface includes a separate line for each current sense circuit coupled to the current sense interface and which is configured to support single-ended or differential current sense. The regulator also includes a plurality of pullup circuits, each of which is connected to one of the current sense interface lines and has a higher impedance than the line to which it is connected. A fault detection circuit of the controller determines if an individual one of the current sense interface lines has an open fault, based on the pullup circuit connected to the line with the open fault pulling up the voltage on the line by more than a predetermined amount.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate that one or more of the power stages is faulty and disabled; communicate the throttling signal to the processor over a physical line running between the processor and the controller; and place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: A multiphase voltage regulator includes a plurality of power stages, a plurality of current sense circuits, a controller and a current sense interface running between the controller and one or more of the current sense circuits. The current sense interface includes a separate line for each current sense circuit coupled to the current sense interface and which is configured to support single-ended or differential current sense. The regulator also includes a plurality of pullup circuits, each of which is connected to one of the current sense interface lines and has a higher impedance than the line to which it is connected. A fault detection circuit of the controller determines if an individual one of the current sense interface lines has an open fault, based on the pullup circuit connected to the line with the open fault pulling up the voltage on the line by more than a predetermined amount.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate if one or more of the power stages is faulty and disabled; and communicate the throttling signal to the processor over a physical line running between the processor and the controller. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: A high-speed, low-latency configurable digital interface for a voltage regulator includes a first hardwired unit, a second hardwired unit and a programmable microcontroller interfaced between the first and second hardwired units. The first hardwired unit is operable to deserialize incoming frames received over the configurable digital interface into commands and data associated with operation of a switching voltage regulator, and serialize outgoing data into new frames for transmission over the configurable digital interface. The second hardwired unit is operable to process the commands included in the incoming frames deserialized by the first hardwired unit, and provide the outgoing data to be serialized into new frames by the first hardwired unit. The programmable microcontroller is operable to change one or more of the commands and data flowing between the first and second hardwired units.

Abstract: A high-speed, low-latency configurable digital interface for a voltage regulator includes a first hardwired unit, a second hardwired unit and a programmable microcontroller interfaced between the first and second hardwired units. The first hardwired unit is operable to deserialize incoming frames received over the configurable digital interface into commands and data associated with operation of a switching voltage regulator, and serialize outgoing data into new frames for transmission over the configurable digital interface. The second hardwired unit is operable to process the commands included in the incoming frames deserialized by the first hardwired unit, and provide the outgoing data to be serialized into new frames by the first hardwired unit. The programmable microcontroller is operable to change one or more of the commands and data flowing between the first and second hardwired units.

Abstract: A method of regulating an output voltage of a buck converter during a startup period in which the buck converter is first enabled includes regulating the output voltage of the buck converter to a reference voltage under current-mode control during a first part of the startup period, and regulating the output voltage of the buck converter to the reference voltage under voltage-mode control during a second, later part of the startup period. The reference voltage ramps up from an initial voltage at the beginning of the startup period to a target voltage at the end of the startup period. Buck converter embodiments are also described.

Abstract: A method of regulating an output voltage of a buck converter during a startup period in which the buck converter is first enabled includes regulating the output voltage of the buck converter to a reference voltage under current-mode control during a first part of the startup period, and regulating the output voltage of the buck converter to the reference voltage under voltage-mode control during a second, later part of the startup period. The reference voltage ramps up from an initial voltage at the beginning of the startup period to a target voltage at the end of the startup period. Buck converter embodiments are also described.

Abstract: A high-speed, low-latency configurable digital interface for a voltage regulator includes a first hardwired unit, a second hardwired unit and a programmable microcontroller interfaced between the first and second hardwired units. The first hardwired unit is operable to deserialize incoming frames received over the configurable digital interface into commands and data associated with operation of a switching voltage regulator, and serialize outgoing data into new frames for transmission over the configurable digital interface. The second hardwired unit is operable to process the commands included in the incoming frames deserialized by the first hardwired unit, and provide the outgoing data to be serialized into new frames by the first hardwired unit. The programmable microcontroller is operable to change one or more of the commands and data flowing between the first and second hardwired units.

Abstract: The invention provides a method for controlling a subscriber line interface circuit, which is connected to at least one data line and to at least one subscriber line associated with a subscriber, in the on-hook state, having the following steps: on-hook data transmission signals are detected in the data line; if an on-hook data transmission signal intended for the subscriber (102) is detected in the data line (122), the detected on-hook data transmission signal is buffer-stored and the subscriber line interface circuit (106) is switched from a passive operating mode to an active operating mode; the buffer-stored detected on-hook data transmission signal is transmitted by the subscriber line interface circuit (106) in the subscriber line (104) to the subscriber (102); and the subscriber line interface circuit (106) is switched to the passive operating mode. The invention also provides a circuit arrangement for carrying out the method.

Abstract: In the broadband network access device for transmitting narrowband, low-frequency voice signals and broadband, higher-frequency data signals, the voice data is sampled in the data clock pattern and subsequently decimated. The transmission of the data which has already been decimated to the voice clock to the voice DSP (DSP) is still carried out in the data clock pattern. The conversion to the voice clock pattern is carried out in a synchronization interface (SM), directly upstream of the voice DSP. The same applies correspondingly in the opposite direction of transmission. The invention is used in xDSL methods, for example ADSL.Lite.

Abstract: The invention creates a method for adjusting a ringing signal current in a subscriber line (106), a ringing signal generator (114) which generates the ringing signal being connected with one end of the subscriber line (106) and at least one subscriber (102) being connected to another end of the subscriber line (106), comprising the steps of detecting a ringing signal current of the ringing signal; of comparing the detected ringing signal current with a predetermined current value; and when the detected ringing signal current is greater than the predetermined current value, reducing a ringing signal voltage of the ringing signal in such a manner that the ringing signal current is equal to the predetermined current value, the ringing signal voltage being dropped across the subscriber line (106) and a load of at least one subscriber (102). The invention also creates a circuit arrangement for carrying out the method.

Abstract: Transceiver for transmitting and receiving voice and data signals includes a voice signal driver configured to operate in idle or working operating modes, during which it has a high or low output impedances respectively. A data signal driver drives an analog data transmission signal via a channel to the subscriber. A data reception circuit that converts a received analog data reception signal into digital reception data includes a multiplication circuit for multiplying the digital reception data by compensation coefficients selected to compensate for channel distortions, an identification circuit connected to the channel for providing an identification signal indicative of whether the subscriber terminal is on or off-hook, and a control circuit to select the operating mode in response to the identification signal and to determine compensation coefficients to compensate for a change in the channel resulting from a change in the output impedance of the voice signal driver.

Abstract: Driver circuit for driving voice and data signals from a switching center via a subscriber line (38) to a subscriber terminal, having: a controllable voice signal driver (12) which has a high output impedance in a quiescent operating mode and, in a working operating mode, drives an analog voice signal from the switching center via the subscriber line (38) to the subscriber terminal, with a low output impedance; a controllable data signal driver, which has a high output impedance in the quiescent operating mode and, in the working operating mode, drives an analog-modulated data signal in a data transmission frequency band (&Dgr;f) from the switching center via the subscriber line (38) to the subscriber terminal; an identification circuit (27), which, in the quiescent operating mode, identifies a current rise in a current flowing via the subscriber line (38) when the subscriber terminal is picked up, and produces a pick-up identification signal; and having a CODEC circuit (4), which, on receiving the pick-u

Abstract: The invention provides a method for controlling a subscriber line interface circuit, which is connected to at least one data line and to at least one subscriber line associated with a subscriber, in the on-hook state, having the following steps: on-hook data transmission signals are detected in the data line; if an on-hook data transmission signal intended for the subscriber (102) is detected in the data line (122), the detected on-hook data transmission signal is buffer-stored and the subscriber line interface circuit (106) is switched from a passive operating mode to an active operating mode; the buffer-stored detected on-hook data transmission signal is transmitted by the subscriber line interface circuit (106) in the subscriber line (104) to the subscriber (102); and the subscriber line interface circuit (106) is switched to the passive operating mode. The invention also provides a circuit arrangement for carrying out the method.

Abstract: The invention creates a method for adjusting a ringing signal current in a subscriber line (106), a ringing signal generator (114) which generates the ringing signal being connected with one end of the subscriber line (106) and at least one subscriber (102) being connected to another end of the subscriber line (106), comprising the steps of detecting a ringing signal current of the ringing signal; of comparing the detected ringing signal current with a predetermined current value; and when the detected ringing signal current is greater than the predetermined current value, reducing a ringing signal voltage of the ringing signal in such a manner that the ringing signal current is equal to the predetermined current value, the ringing signal voltage being dropped across the subscriber line (106) and a load of at least one subscriber (102). The invention also creates a circuit arrangement for carrying out the method.

Abstract: Codec circuit for increasing the data transmission rate in a modem transmission with a first programmable digital filter (13) which is connected into a transmission signal path of the Codec circuit, a second programmable digital filter (22) which is connected into a reception signal path of the Codec circuit, a modem signal detection device (31) for detecting whether the transmission signal which is output on the transmission signal path or the reception signal which is received on the reception signal path is a modem signal, the modem signal detection device (31) switching the first and second digital filters (13, 22) to a widened filter bandwidth when a modem signal is detected.

Abstract: Method for measuring a load impedance (ZL) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal device, having the following steps: specifically a digital toll signal (x1) is generated by means of a Codec circuit (13) connected to the SLIC circuit (6), said toll signal (x1) being converted into an analog toll signal; the analog toll signal is output by the SLIC circuit (6) to the load circuit; an analog voltage which is brought about at the terminal connection (4,5) of the terminal device of the SLIC circuit (6) via the analog toll signal is sensed; the digital toll signal (x1) is filtered by means of an adaptive filter (39) which is provided in the Codec circuit (13) and has adjustable filter coefficients (g1, g2) for generating a filtered digital comparison signal (yv) which is converted into an analog comparison voltage (Uv); the filter coefficients (g1, g2) of the adaptive filter (39) are adjusted until the analog comparison voltage (Uv) and the analog