Abstract: An arithmetic logic unit capable of performing AND, OR, exclusive-OR, and add functions is implemented utilizing strobed gates. An input section receives first and second inputs, each capable of assuming first and second states, and generates a first output indicating that at least one of the inputs is in a first state and a second output indicating that both inputs are in the first state. First, second and third strings of field-effect-transistors controlled by a plurality of control signals are selectively enabled respectively when at least one of the inputs is in the first state, all of the inputs are in the first state, or when only one of the inputs is in the first state. The circuit includes an output section and a circuit for generating a carry-out signal when the inputs so require.

Abstract: A data processor for performing a division operation requiring shifting and the counting of the number of shifts, having no dedicated counters therefor. An additional shift left path from the temporary register of the previous bit to the next bit address bus is the only extra circuitry added, which greatly simplifies the shift left circuit of the temporary register. In addition, the dedicated counter may be eliminated as a formerly idle address incrementer circuit now performs the shift left and count functions. Not only are formerly idle registers now being used for lengthy shifting and cycle counting operations, but an overall savings in chip area is recognized, since the dedicated counter is eliminated and the dedicated shifter is greatly simplified.

Abstract: A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.

Abstract: A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

Abstract: A static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing a logic low at the control node. Only a single P channel device is required because it can be made to have sufficiently low gain at a relatively small device size so that the control node can have it logic state switched by an N channel device of comparable size.

Abstract: A CMOS Schmitt trigger which has two series-connected inverters uses both an input and an output signal to provide hysteresis. A pair of series-coupled transistors is coupled between a power supply terminal and a node between the two inverters. One of the transistors has a control electrode for receiving the input signal. The other of the transistors has a control electrode for receiving the output signal.

Abstract: A control state sequencer for controlling the execution of instructions of a microprocessor uses a PLA and a ROM to detect the current control state and instruction being processed by a processing unit and to provide the next control state of the instruction to the processing unit. An initial-state PLA and initial-state ROM detect when a new instruction is to be processed by the processing unit and provides the initial clock state of the new instruction to the processing unit.

Abstract: Wafers of silicon semiconductor material are stacked, bonded and severed to form a plurality of semiconductor diodes. One or more capacitor bodies are physically and electrically joined with these diodes, either by means of the capacitor bodies themselves or by means of an intermediate lead frame structure, in order to facilitate the handling and processing of the assembly as a unit.