Patents by Inventor Herman CHEUNG
Herman CHEUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10396800Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: GrantFiled: October 9, 2018Date of Patent: August 27, 2019Assignee: AnDAPT, Inc.Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Patent number: 10320391Abstract: A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: GrantFiled: October 9, 2018Date of Patent: June 11, 2019Assignee: AnDAPT, Inc.Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Patent number: 10312911Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.Type: GrantFiled: May 18, 2018Date of Patent: June 4, 2019Assignee: AnDAPT, Inc.Inventors: John Birkner, Kapil Shankar, Herman Cheung, Patrick J. Crotty, Ranajit Ghoman
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Publication number: 20190052275Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: ApplicationFiled: October 9, 2018Publication date: February 14, 2019Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Publication number: 20190052272Abstract: A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: ApplicationFiled: October 9, 2018Publication date: February 14, 2019Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Patent number: 10200056Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.Type: GrantFiled: May 11, 2018Date of Patent: February 5, 2019Assignee: AnDAPT, Inc.Inventors: Maheen Samad, Patrick J. Crotty, John Birkner, Herman Cheung, Kapil Shankar
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Patent number: 10141937Abstract: A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: GrantFiled: August 9, 2017Date of Patent: November 27, 2018Assignee: ANDAPT, INC.Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Patent number: 10135447Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: GrantFiled: July 21, 2017Date of Patent: November 20, 2018Assignee: ANDAPT, INC.Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Publication number: 20180269876Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper.Type: ApplicationFiled: May 18, 2018Publication date: September 20, 2018Inventors: John BIRKNER, Kapil SHANKAR, Herman CHEUNG, Patrick J. CROTTY, Ranajit GHOMAN
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Publication number: 20180262202Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.Type: ApplicationFiled: May 11, 2018Publication date: September 13, 2018Inventors: Maheen SAMAD, Patrick J. CROTTY, John BIRKNER, Herman CHEUNG, Kapil SHANKAR
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Patent number: 10003338Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.Type: GrantFiled: July 21, 2017Date of Patent: June 19, 2018Assignee: AnDAPT, INC.Inventors: John Birkner, Kapil Shankar, Herman Cheung, Patrick J. Crotty, Ranajit Ghoman
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Patent number: 9998135Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.Type: GrantFiled: August 9, 2017Date of Patent: June 12, 2018Assignee: AnDAPT, INC.Inventors: Maheen Samad, Patrick J. Crotty, John Birkner, Herman Cheung, Kapil Shankar
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Publication number: 20180048324Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.Type: ApplicationFiled: August 9, 2017Publication date: February 15, 2018Inventors: Maheen Samad, Patrick J. Crotty, John Birkner, Herman Cheung, Kapil Shankar
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Publication number: 20180048318Abstract: A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: ApplicationFiled: August 9, 2017Publication date: February 15, 2018Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
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Publication number: 20180026636Abstract: A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programmable fabric and the signal wrapper.Type: ApplicationFiled: July 21, 2017Publication date: January 25, 2018Inventors: John BIRKNER, Kapil SHANKAR, Herman CHEUNG, Patrick J. CROTTY, Ranajit GHOMAN
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Publication number: 20180026644Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.Type: ApplicationFiled: July 21, 2017Publication date: January 25, 2018Inventors: Kapil SHANKAR, Herman CHEUNG, John BIRKNER, Patrick J. Crotty