Abstract: Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system.

Abstract: Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system.

Abstract: Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system.

Abstract: Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system.

Abstract: Mechanisms for controlling rollover or reset of hardware performance counters in the data processing system. A signal indicating that a rollover or reset of a first hardware performance counter has occurred is received and it is determined if the first hardware performance counter is analytically related to one or more second hardware performance counters based on defined ganged hardware performance counter sets. A signal is sent to each of the one or more second hardware performance counters in response to a determination that the first hardware performance counter is analytically related to the one or more second hardware performance counters. Each of the one or more second hardware performance counters is reset to an initial value in response to the one or more second hardware performance counters receiving the signal from the ganged hardware performance counter rollover/reset logic.

Abstract: Mechanisms for controlling rollover or reset of hardware performance counters in the data processing system. A signal indicating that a rollover or reset of a first hardware performance counter has occurred is received and it is determined if the first hardware performance counter is analytically related to one or more second hardware performance counters based on defined ganged hardware performance counter sets. A signal is sent to each of the one or more second hardware performance counters in response to a determination that the first hardware performance counter is analytically related to the one or more second hardware performance counters. Each of the one or more second hardware performance counters is reset to an initial value in response to the one or more second hardware performance counters receiving the signal from the ganged hardware performance counter rollover/reset logic.

Abstract: Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

Abstract: Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission.