Abstract: According to the present invention, an input buffer is utilized to first amplify a differential clock or data signal pair to a desired voltage level before being presented to a CMOS or NMOS differential amplifier. In a preferred embodiment of the present invention, a PECL input buffer is comprised of a plurality of n-channel transistors which are capable of quickly amplifying the voltage level of the differential input signal pair.

Abstract: According to the present invention, synchronization between two or more asynchronous devices or systems is accomplished according to the clock edges of the asynchronous devices or systems rather synchronization through sampling of the clock frequencies of the asynchronous devices or systems. Because synchronization is dependent on the clock edges rather than frequencies, there are two readily apparent advantages. First, it is no longer necessary to sample data in order to determine frequencies of the asynchronous devices or systems. Second, the data transmitted from a transmitter device, such as a microprocessor, to a receiver device, such as a printer, can be assured of being stable data before being received by the receiver device. Because the data received by the receiver device is not in transition or otherwise meta-stable, it is valid, uncorrupted data.