Patents by Inventor Herman Lee Blackmon
Herman Lee Blackmon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8549217Abstract: A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.Type: GrantFiled: November 17, 2009Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Ronald Ernest Freking, Ryan Scott Haraden, Joseph Allen Kirscht
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Patent number: 8082396Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.Type: GrantFiled: April 28, 2005Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Philip Rogers Hillier, III, Joseph Allen Kirscht, Brian T. Vanderpool
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Publication number: 20110119439Abstract: A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.Type: ApplicationFiled: November 17, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herman Lee Blackmon, Ronald Ernest Freking, Ryan Scott Haraden, Joseph Allen Kirscht
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Patent number: 6963516Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.Type: GrantFiled: November 27, 2002Date of Patent: November 8, 2005Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, John Michael Borkenhagen, Joseph Allen Kirscht, James Anthony Marcella, David Alan Shedivy
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Patent number: 6895482Abstract: An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution.Type: GrantFiled: September 10, 1999Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Publication number: 20040103258Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herman Lee Blackmon, John Michael Borkenhagen, Joseph Allen Kirscht, James Anthony Marcella, David Alan Shedivy
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Patent number: 6628662Abstract: A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred.Type: GrantFiled: November 29, 1999Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6523080Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.Type: GrantFiled: January 27, 1998Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David John Krolak, James Anthony Marcella, Peder James Paulson
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Patent number: 6513091Abstract: A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.Type: GrantFiled: November 12, 1999Date of Patent: January 28, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6505306Abstract: An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.Type: GrantFiled: September 15, 1999Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella
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Patent number: 6188627Abstract: A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than the entire DRAM array provides a lower latency than existing full DRAM burst techniques.Type: GrantFiled: August 13, 1999Date of Patent: February 13, 2001Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Kent Harold Haselhorst, William Paul Hovis, James Anthony Marcella
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Patent number: 5748919Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.Type: GrantFiled: July 10, 1996Date of Patent: May 5, 1998Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David John Krolak, James Anthony Marcella, Peder James Paulson