Patents by Inventor Hermana Wilhelmina Hendrika De Groot

Hermana Wilhelmina Hendrika De Groot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device for exchanging data signals between two clock domains
    Patent number: 7392417
    Abstract: A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of the data signals.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 24, 2008
    Assignee: NXP B.V.
    Inventors: Hermana Wilhelmina Hendrika De Groot, Roland Mattheus Maria Hendricus Van Der Tuijn
  • DC-offset correction circuit having a DC control loop and a DC blocking circuit
    Patent number: 7233631
    Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: June 19, 2007
    Assignee: NXP B.V.
    Inventors: Adrianus Van Bezooijen, Marc Victor Arends, Hermana Wilhelmina Hendrika De Groot
  • DC-offset correction circuit having a DC control loop and a DC blocking circuit
    Publication number: 20020075892
    Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.
    Type: Application
    Filed: November 19, 2001
    Publication date: June 20, 2002
    Inventors: Adrianus Van Bezooijen, Marc Victor Arends, Hermana Wilhelmina Hendrika De Groot