Abstract: In a process for manufacturing a semiconductor arrangement, wherein an uneven surface of the semiconductor arrangement is smoothened, there is produced on the uneven surface an insulating layer of such thickness that the insulating layer produced on the surface exhibits an even surface. The insulating layer is then partially removed again.

Abstract: A method of manufacturing an integrated circuit including an analog circuit and an I.sup.2 L circuit which both contain NPN transistors on a P-type semiconductor chip in which the method includes an N.sup.+ diffusion step for producing a flat diffusion for certain NPN transistors having smaller penetration depth than N.sup.+ regions of the other NPN transistors for connection of an emitter electrode to the said certain NPN transistors.

Abstract: A monolithic integrated semiconductor circuit including a plurality of low on-state resistance vertical bipolar switching transistors for connecting a series of input lines, as desired, to one or more output lines wherein each of said switching transistors comprises a substrate region of a first type of conductivity having a first layer thereon of the second type of conductivity, a second layer on the first layer and of the second type of conductivity but with a lower doping than the first layer, a third layer of the first type of conductivity in the second layer, a fourth layer of the second type of conductivity in the third layer, a tank like structure formed from the first layer and a region encircling the second third and fourth layers and of the second type of conductivity, a first frame like region of the second type of conductivity encircling the tank like structure, a second frame like region encircling the first frame like region and being of the first type of conductivity and in contact with the sub