Patents by Inventor Hermann W. Gartler
Hermann W. Gartler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10678712Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: GrantFiled: February 11, 2019Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
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Publication number: 20190188158Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: Robert S. Chappell, John W. FAISTL, Hermann W. GARTLER, Michael D. TUCKNOTT, Rajesh S. PARTHASARATHY, David W. Burns
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Patent number: 10216650Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: GrantFiled: January 29, 2018Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
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Patent number: 10198333Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.Type: GrantFiled: December 23, 2010Date of Patent: February 5, 2019Assignee: INTEL CORPORATIONInventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Brian Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
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Publication number: 20180225228Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: ApplicationFiled: January 29, 2018Publication date: August 9, 2018Inventors: ROBERT S. CHAPPELL, JOHN W. FAISTL, HERMANN W. GARTLER, MICHAEL D. TUCKNOTT, RAJESH S. PARTHASARATHY, DAVID W. BURNS
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Patent number: 9880948Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: GrantFiled: December 19, 2016Date of Patent: January 30, 2018Assignee: INTEL CORPORATIONInventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parthasarathy, David W. Burns
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Patent number: 9759768Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.Type: GrantFiled: August 26, 2016Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Michael Neve De Mevergnies, Hermann W. Gartler, Michael S. Bair
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Publication number: 20170097902Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: ApplicationFiled: December 19, 2016Publication date: April 6, 2017Inventors: ROBERT S. CHAPPELL, JOHN W. FAISTL, HERMANN W. GARTLER, MICHAEL D. TUCKNOTT, RAJESH S. PARTHASARATHY, DAVID W. BURNS
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Patent number: 9524263Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: GrantFiled: June 29, 2012Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns
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Publication number: 20160363624Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Michael Neve De Mevergnies, Hermann W. Gartler, Michael S. Bair
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Patent number: 9430347Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.Type: GrantFiled: December 23, 2014Date of Patent: August 30, 2016Assignee: Intel CorporationInventors: Michael Neve De Mevergnies, Hermann W. Gartler, Michael S. Bair
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Publication number: 20160179646Abstract: A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Michael Neve De Mevergnies, Hermann W. Gartler, Michael S. Bair
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Publication number: 20150127983Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.Type: ApplicationFiled: December 23, 2010Publication date: May 7, 2015Applicant: INTEL CORPORATIONInventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Briar Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
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Patent number: 8683158Abstract: Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.Type: GrantFiled: December 30, 2005Date of Patent: March 25, 2014Assignee: Intel CorporationInventors: Martin G. Dixon, David A. Koufaty, Camron B. Rust, Hermann W. Gartler, Frank Binns
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Publication number: 20140006661Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns
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Patent number: 7502892Abstract: Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not retrieved and the cache line may be updated if, based on the tag, the cache line is determined to be in a modified or exclusive state.Type: GrantFiled: December 30, 2003Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Per H. Hammarlund, Hermann W. Gartler