Abstract: A modular compute platform including an enclosure, a first module including an application specific integrated circuit, the first module being disposed in the enclosure, a second module including an input/output device, the second module being disposed in the enclosure, the input/output device connected to the first module through a first cable, and a third module including a media device disposed in the enclosure, the media device connected to the first module through a second cable.

Abstract: Examples relate to a modular server architecture that comprises a server chassis, a plurality of independent resource modules releasable attached to the server chassis a memory semantic protocol controller connected to the plurality of independent resource modules. Each one of the resource modules of the plurality of resource modules has a distinct Printed Circuit Board (PCB). The memory semantic media controller is to manage the plurality of independent resource modules.

Abstract: A modular compute platform including an enclosure, a first module including an application specific integrated circuit, the first module being disposed in the enclosure, a second module including an input/output device, the second module being disposed in the enclosure, the input/output device connected to the first module through a first cable, and a third module including a media device disposed in the enclosure, the media device connected to the first module through a second cable.

Abstract: Examples relate to a modular server architecture that comprises a server chassis, a plurality of independent resource modules releasable attached to the server chassis a memory semantic protocol controller connected to the plurality of independent resource modules. Each one of the resource modules of the plurality of resource modules has a distinct Printed Circuit Board (PCB). The memory semantic media controller is to manage the plurality of independent resource modules.

Abstract: A die includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch.

Abstract: A die includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch.

Abstract: Redundancy is provided in a memory device having a configurable data bus organization by associating a redundant memory location with a defective memory location and configuring a size of the redundant memory location based on the current data bus organization of the memory device.

Abstract: Fuse sensing is performed in an integrated circuit by selecting a reference voltage based on a temperature measurement acquired by the integrated circuit. A state of one or more fuses included in the integrated circuit is sensed based on the reference voltage during normal operation of the integrated circuit. The state of the one or more fuses may be sensed during testing of the integrated circuit based on a different reference voltage.