Abstract: It is known in charge coupled devices to use a dual layer of silicon oxide and silicon nitride as the gate dielectric. Since silicon nitride is practically impermeable to hydrogen, the nitride layer is usually provided with openings through which hydrogen can penetrate up to the surface of the silicon body during the annealing step carried out for passivating the surface. The openings in the nitride layer are provided by a known method, with gates in a first poly layer serving as a mask, in that the nitride is removed from between these gates and an oxidation step is subsequently carried out. According to the invention, the openings in the nitride layer are formed by means of a separate mask (20), such that the edges of the openings (9) in the nitride layer (8) lie at some distance from the edges of the gates.

Abstract: It may be necessary to provide conductors at very small distances from one another when electronic circuits, for example integrated circuits, are manufactured on an insulating substrate. A multilayer wiring system is often used in that case. The invention renders it possible to make very small inter-electrode gaps in a single conductor layer. To achieve this, the conductor layer is covered with a comparatively thick dielectric layer 4, 5 in which windows 8 are formed which extend over only part of the dielectric layer. Then an auxiliary layer 9 is provided which has depressions at the areas of the windows 8. Windows 11 are formed in the dielectric layer by anisotropic etching-back with dimensions which are substantially smaller than the dimensions of the original windows 8. The windows 11 may be used as etching windows or oxidation windows for the subsequent formation of the definitive conductor pattern.

Abstract: Method of manufacturing a semiconductor device and semiconductor device manufactured by such a method.A method of manufacturing a semiconductor device whereby a surface of a semiconductor body 1 is covered with an electrically insulating layer 8 and at least two electrical conductors 20, 23 are provided on the insulating layer next to one another and mutually separated by an interposed dielectric layer 21. The conductor 20 is formed from a first conductive layer deposited on the insulating layer. The upper surface and at least the flank 25 of the conductor 20 facing the other conductor are covered with the dielectric layer 21. Then a second conductive layer 22 is deposited over the entire surface which exhibits a step corresponding to the flank 25 of the first conductor. Subsequently, a mask 24 is formed which defines the second conductor, after which the second conductor 23 is formed from the second conductive layer through etching.

Abstract: An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, a conductive etching stopper layer is provided in the oxide layer. A layer already present in the process is used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.

Abstract: A 3-phase charge-coupled imaging device is operated in the interlace mode. During integration, voltages are applied to the clock electrodes such that charge is integrated below the same set of electrodes each time. The signal charges of the first field are formed in that 3/4 portion of the charge in each picture element is augmented by 1/4 portion of the charge of the preceding picture element, while the signal charges of the second field are formed in that the 3/4 portion is augmented by 1/4 portion of the charge generated in the following picture element. These summations may be carried out in the sensor itself in that the charge packages are shifted to the left and right during integration. The flicker which is usually the result of interlacing is very strongly reduced in this way.

Abstract: In charge coupled imaging devices, a major portion of the photosensitive surface area is covered by electrodes with which the charge storage and the charge transport in the semiconductor body are controlled. These electrodes are preferably made of polycrystalline silicon. This material, however, like other conductive materials known per se, has a comparatively high absorption coefficient, in particular in the short-wave portion of the visible spectrum (blue), which adversely affects the sensitivity. According to the invention, the electrodes are manufactured partly from a very thin poly layer, preferably not thicker than 50 nm, and partly from a less transparent but higher conductivity layer, for example, poly of much greater thickness.

Abstract: An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, an etching stopper layer is provided in the oxide layer. A layer already present in the process may be used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.

Abstract: For manufacturing an implantation mask on a semiconductor surface which is provided with grooves, a positive photoresist is provided on the surface. Portions of the photoresist which are to form the implantation mask are illuminated in a first step and rendered insoluble in the developer in an image reversal step. The photoresist is then illuminated without mask and developed, so that the portions not illuminated during the first step are removed. The implantation mask thus obtained has a receding profile, the openings at the area of the grooves becoming wider in the direction of the bottom of the grooves.

Abstract: A semiconductor device comprising a semiconductor body (1) having a surface (2) provided with a first insulating layer (3). On this layer is disposed a pattern of conductor strips (4) coated with insulation strips (5) with projecting edges (6). Under the edges (6), the conductor strips (4) are coated with insulating tracks (8) which fill the spaces under the edges (6) and which at least at the area where they adjoin the first insulating layer (3) can be etched selectively with respect to this layer (3). As a material for the conductor strips (4) use may be made of materials other than polycrystalline silicon, such as tungsten, molybdenum and silicides. The thickness of the first insulating layer (3) is affected to a very small extent during the manufacture of the device, while its depth remains unchanged.

Abstract: A semiconductor device comprises a semiconductor body having a surface provided with a first insulating layer. On this first insulating layer at least one pattern of conductor strips, coated with insulation strips having projecting edges, is provided. Under projecting edges of a second insulating layer, the conductor strips are coated with insulating tracks which fill the spaces under the edges and which at least at the area where they adjoin the first insulating layer can be selectively etched with respect to this layer. The conductor strips may be made of materials other than polycrystalline silicon, such as tungsten, molybdenum, and silicides of these metals. The thickness of the first insulating layer is affected to a very small extent during manufacture of the device, while its depth remains unchanged.

Abstract: A method of manufacturing a semiconductor device having at least one narrow and comparatively deep groove (3) in the semiconductor surface, while zones (9) are implanted in the walls and/or the bottom of the groove over only part of the groove length. According to the invention, the implantation mask is provided on a filler material (6), which fills the groove and is removed after the masking layer (7) has been provided. The filler material preferably consists of a photo-resist.

Abstract: A method is set forth of manufacturing a three-layer electrode system, more particularly for use in CCD image sensors. A group of first electrodes (4A,B,C) is formed on a gate oxide layer (3) by a first silicon layer (4). After etching away the exposed gate oxide, a first thermal oxidation is carried out. Subsequently, an anti-oxidation layer (6) of, for example, silicon nitride is provided, on which a second silicon layer (7) is provided, from which a group of second electrodes (7A,B) is formed. The second electrode overlap the first electrodes in part, whereupon they are subjected to a second thermal oxidation. The exposed part of the anti-oxidation layer (6) is removed by anisotropic plasma etching which maintains parts (6A) on the edge of the first electrodes and under projecting oxide edges. After a third thermal oxidation, a third silicon layer (9) is provided, from which a third group of electrodes (9A,B) is formed, which partially overlap first and second electrodes.

Abstract: In manufacturing a semiconductor device, a semiconductor body (2) is first provided with a first insulating layer (3,4) having a homogeneous dielectric thickness. A first conductor pattern (5) of polycrystalline silicon is then provided on the first insulating layer. A second insulating layer (6) is formed by oxidation of the first conductor pattern in such manner that the dielectric thickness of the first insulating layer remains approximately constant. Insulating paths (8) are then formed in spaces below edges (9) of the second insulating layer by successive deposition and etching steps. During the deposition step, a temporary layer is deposited to a thickness exceeding half the height of the spaces. During the etching step, the temporary layer is removed from the second insulating layer. Finally, a second conductor pattern (7) is provided on and beside the second insulating layer.

Abstract: A method is set forth for providing on a substrate surface a conductor pattern having portions which are present at a mutual separation distance smaller than 10 microns by directed deposition of the material for the conductor portions in different directions through a mask which has apertures present comparatively closely beside each other. The mask is arranged at a small distance above the substrate surface. This method is suitable in particular for use in manufacturing semiconductor devices, for example, charge transfer devices.