Patents by Inventor Hernan A. Rueda

Hernan A. Rueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672703
    Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 2, 2020
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Hernan Rueda, Humayun Kabir
  • Patent number: 10644148
    Abstract: An active semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, includes a substrate having a substrate resistivity of at least 1 kohm-cm. An active area of the active semiconductor device is formed in the substrate. A doped implant region is formed in the substrate surrounding the active area of the active semiconductor device and a field oxide region is formed over the doped implant region. The doped implant region may include a boron dopant. Methodology entails forming the doped implant region prior to formation of the field oxide region.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 5, 2020
    Assignee: NXP USA, Inc.
    Inventors: Xiaowei Ren, Hernan Rueda, Rodney Arlan Barksdale
  • Publication number: 20200098683
    Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Vikas Shilimkar, Kevin Kim, Hernan Rueda, Humayun Kabir
  • Patent number: 10593619
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 17, 2020
    Assignee: NSP USA, Inc.
    Inventors: Ibrahim Khalil, Charles John Lessard, Damon G. Holmes, Hernan Rueda
  • Publication number: 20200075479
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: Ibrahim Khalil, Charles John Lessard, Damon G. Holmes, Hernan Rueda
  • Publication number: 20190378923
    Abstract: An active semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, includes a substrate having a substrate resistivity of at least 1 kohm-cm. An active area of the active semiconductor device is formed in the substrate. A doped implant region is formed in the substrate surrounding the active area of the active semiconductor device and a field oxide region is formed over the doped implant region. The doped implant region may include a boron dopant. Methodology entails forming the doped implant region prior to formation of the field oxide region.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: Xiaowei Ren, Hernan Rueda, Rodney Arlan Barksdale
  • Patent number: 10147686
    Abstract: A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of layers of dielectric material and electrically conductive material on the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure positioned between the pillar and the tap interconnect formed from the electrically conductive material and extending through the dielectric material. The pillar contacts the first terminal and connects to a first runner. The tap interconnect contacts the second terminal and connects to a second runner. The shield structure includes a base segment, a first leg, and a second leg extending from opposing ends of the base segment, wherein the first and second legs extend from opposing ends of the base segment in a direction that is antiparallel to a length of the base segment.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 4, 2018
    Assignee: NXP USA, Inc.
    Inventors: Charles John Lessard, Damon G. Holmes, David Cobb Burdeaux, Hernan Rueda, Ibrahim Khalil
  • Patent number: 10103233
    Abstract: An embodiment of a transistor die includes a semiconductor substrate a drain region, a channel region, a drain terminal, and a conductive gate tap. The conductive gate tap includes a distal end that is coupled to a gate structure over the channel region. A first segment of the drain region is adjacent to the distal end of the gate tap. The drain terminal includes a drain runner formed from one or more portions of the patterned conductive layers. A plurality of drain pillars electrically connects the drain runner to second and third segments of the drain region, and a plurality of second drain pillars electrically connect the drain runner and the third drain region segment. The build-up structure over the second drain region segment between the first and second drain pillars is devoid of electrical connections between the drain runner and the drain region.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 16, 2018
    Assignee: NXP USA, INC.
    Inventors: Ibrahim Khalil, David Cobb Burdeaux, Damon Holmes, Hernan Rueda, Partha Sarathi Chakraborty
  • Patent number: 9818862
    Abstract: A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the guard region. The floating field plates and guard region act in some embodiments to “smooth” the electrical field distribution along the termination area.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Zihao M. Gao, David C. Burdeaux, Wayne Robert Burger, Christopher P. Dragon, Hernan A. Rueda
  • Publication number: 20170194488
    Abstract: A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the guard region. The floating field plates and guard region act in some embodiments to “smooth” the electrical field distribution along the termination area.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: ZIHAO M. GAO, DAVID C. BURDEAUX, WAYNE ROBERT BURGER, CHRISTOPHER P. DRAGON, HERNAN A. RUEDA
  • Patent number: 9653410
    Abstract: A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of multiple layers of dielectric material and electrically conductive material on an upper surface of the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure formed from the electrically conductive material. The pillar electrically contacts the first terminal, extends through the dielectric material, and connects to a first runner. The tap interconnect electrically contacts the second terminal, extends through the dielectric material, and connects to a second runner. The shield structure extends from a shield runner through the dielectric material toward the semiconductor substrate. The shield structure is positioned between the pillar and the tap interconnect to limit feedback capacitance between the tap interconnect and the pillar.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: May 16, 2017
    Assignee: NXP USA, Inc.
    Inventors: Damon Holmes, David Burdeaux, Partha Chakraborty, Ibrahim Khalil, Hernan Rueda
  • Patent number: 8518764
    Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: August 27, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thuy B. Dao, Joel E. Keys, Hernan A. Rueda, Paul W. Sanders
  • Publication number: 20130099312
    Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Inventors: Thuy B. Dao, Joel E. Keys, Hernan A. Rueda, Paul W. Sanders
  • Patent number: 8324064
    Abstract: Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 4, 2012
    Assignee: Freescale Semiconductors, Inc.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Publication number: 20120021586
    Abstract: Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Publication number: 20110031588
    Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).
    Type: Application
    Filed: August 6, 2009
    Publication date: February 10, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Pamela J. Welch, Wen Ling Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi