Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Abstract: A memory sub-system configured to perform multiplication and accumulation operations using truncated outputs. For example, voltages can be applied, according to a bit slice having a slice weight in an input, to memory cells storing weights. A resolution control can be applied, according to the slice weight, to an analog to digital converter coupled to the line having a current resulting from the memory cells responsive to the voltages. The analog to digital converter can measure at least one first bit of a quantity representative of a magnitude of the current in the line to provide a truncated output, skipping measuring of at least one second bit of the quantity according to the resolution control. Summing truncated outputs resulting from the bit slices from the input can provide an approximated result of the sum of elements in the input weighted by the weights.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells stacked vertically above a semiconductor substrate. Each memory cell stores a weight. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells. In one example, each memory cell is formed using a transistor that includes a semiconductor layer to provide a horizontal channel. A gate layer (e.g., a gate stack layer) wraps around a circumference of the semiconductor layer. Wordlines apply gate voltages to the transistors. Each wordline has a respective portion that wraps around a circumference of the gate layer of each transistor.

Abstract: Systems, methods, and apparatus related to memory devices that use multi-pillar memory cells for performing multiplication and other operations. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. The memory cells are arranged in pillars of memory cells connected in series. Each memory cell uses at least one transistor from two or more different pillars. A bitline is formed overlying the pillars. The bitline is electrically connected to the pillars and accumulates output currents from the pillars when performing the matrix vector multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells programmed to have different thresholds based on bit significance. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply voltages to the memory cells. The applied voltages represent inputs to be multiplied by the weights. A common line is coupled each of the memory cells to accumulate output currents from the cells. The output currents each have a magnitude corresponding to the significance of the bit stored by the respective memory cell. A digitizer uses the summed output currents as an input and provides a digital result as an output.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of four memory cells. In one approach, memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are summed in first and second lines. A sum of the output currents in each line is digitized to provide first and second results. The first and second results are combined to provide a signed result for each set.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. In one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or ?1). Voltages that represent signed inputs (e.g., +1, 0, or ?1) are applied to the memory cells to perform the multiplication. A result from the multiplication is determined based on summing of output currents from the memory cells.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logic states of memory cells. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply different voltages to the memory cells during multiplication. The magnitudes of the different voltages correspond to a significance of the bit stored by the respective memory cell. One or more inputs are applied to the memory cells to multiply the inputs by the multi-bit weight. Output currents from the memory cells are summed on a common line. The sum of the output currents is used to provide at least one result from the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of memory cells. In one approach, memory cells in the sets are programmed so that each set stores a signed weight. Voltage drivers apply voltages to the memory cells in each set. The voltages correspond to signed inputs to multiply by the signed weights in the sets. One or more common lines (e.g., bitlines) are coupled to each set for summing output currents from the sets. A digitizer provides a signed result based on summing the output currents from the sets.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a first integrated circuit die has a memory cell array. The memory cell array includes memory cells programmable to store weights (e.g., representing synapses of a neural network). A second integrated circuit die has logic circuitry that performs multiplication of the stored weights by an input pattern. The second die is connected to the first die by hybrid bonding. Multiplication results are determined by the logic circuitry based on accumulation of output currents from at least a portion of the memory cells.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using sets each containing two memory cells. In one approach, sets organized as pairs of memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells at first and second times. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are accumulated at the first and second times in a respective common line for each set. A signed result for each set is provided based on digitizing sums of the output currents accumulated at the first and second times.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multi-bit to multi-bit multiplication using sets of memory cells. In one approach, a memory cell array has sets of memory cells. Each set is programmable to store a multi-bit signed weight. Voltage drivers apply voltages to each set. The voltages correspond to multi-bit signed inputs. One or more common lines are coupled to each set for summing output currents from the sets during the multiplication. A digitizer provides signed results based on summing the output currents. The signed results are added with adjustment for the bit significance of each signed result to provide a final accumulation result for the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.