Abstract: Systems, methods, and apparatus for memory devices that perform multiplication using three-dimensional NAND flash memory cells with horizontal channels. In one approach, memory cells in a string share a common semiconductor channel layer. Read word lines are located on a first side of the channel layer. Write word lines are located on an opposite second side of the channel layer. The read word lines are used to apply read voltages to selected memory cells and pass voltages to non-selected memory cells when performing multiplication. The write word lines are used to program the memory cells when storing weights for a neural network.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory array stores synaptic weights in memory cells. A controller updates the weights by incrementally changing the threshold voltages of the memory cells in a same direction of change. This permits parallel updates of the weights. Each parallel update is performed in two phases of cell programming.

Abstract: Systems, methods, and apparatus for DRAM devices that perform computations for artificial intelligence models. In one approach, a DRAM device stores weights in target memory cells. The DRAM device includes mirror cells that store an identical state of charge stored by corresponding ones of the target memory cells. During a matrix vector multiplication operation, a controller accumulates charge stored in the target memory cells. The accumulated charge is used to provide a result. After accumulating the charge to provide the result, the controller restores the target memory cells to their original state based on the charge stored in the corresponding one of the mirror cells.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication. In one approach, multiple synapses are connected to digit lines used to accumulate charge from memory cells of each synapse. Each synapse includes positive and negative side memory cells. The memory cells are populated with values to use during multiplication. The values are configured based on the polarities of a signed weight stored by the synapse and a signed input signal to be applied to the synapse during the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory array stores weights in memory cells using unary coding. A controller performs matrix vector multiplication using the weights. The multiplication is performed by accumulating output currents from the memory cells onto a common line (e.g., a digit line). The accumulated output currents are converted to a digital result (e.g., using an analog-to-digital converter).

Abstract: Systems, methods, and apparatus for memory devices having shunting networks connected to access lines. In one approach, a memory device has memory cells arranged in a memory array. The memory cells are accessed using bitlines that are formed overlying the array. The bitlines are coupled to a shunting network that reduces the effective resistance of the bitlines. This improves performance when performing matrix vector multiplication using the memory array.

Abstract: Systems, methods, and apparatus for memory devices. In one approach, a memory device has memory cells arranged in a three-dimensional vertical memory array. The memory cells are accessed using bitlines that are formed overlying the array. A controller determines a context of the memory cells. Based on the context, each memory cell is programmed to have an output current that corresponds to a stored weight. Output currents from the memory cells are accumulated using the bitlines for performing matrix vector multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells arranged vertically above a semiconductor substrate. Each memory cell stores a weight using a ferroelectric tunnel junction (FTJ) device as a storage element. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells.

Abstract: Systems, methods, and apparatus for memory devices that apply a fixed gate bias to memory cells during programming and multiplication. In one approach, a fixed voltage bias is applied to gates of the memory cells when the cells are programmed. Output currents from the memory cells are measured to control the extent of the programming. A target output current is used for determining when to end programming and corresponds to a weight to be stored. After programming, inputs are applied to the memory cells, and output currents from the memory cells are accumulated to perform matrix vector multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Abstract: A memory device having: a first local digit line configured to extend in a first direction; a second local digit line configured in parallel with the first local digit line; a plurality of unit cells stacked in the first direction and sandwiched between the first local digit line and the second local digit line, each respective unit cell among the plurality of unit cells configured to connect the first local digit line to the second local digit line in a second direction that is perpendicular to the first direction, the respective unit cell having a transistor and a memory cell; and a plurality of wordlines configured to extend in a third direction that is perpendicular to the first direction and the second direction, where transistors in the plurality of unit cells are connected to the wordlines.

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Abstract: A memory sub-system configured to perform multiplication and accumulation operations using truncated outputs. For example, voltages can be applied, according to a bit slice having a slice weight in an input, to memory cells storing weights. A resolution control can be applied, according to the slice weight, to an analog to digital converter coupled to the line having a current resulting from the memory cells responsive to the voltages. The analog to digital converter can measure at least one first bit of a quantity representative of a magnitude of the current in the line to provide a truncated output, skipping measuring of at least one second bit of the quantity according to the resolution control. Summing truncated outputs resulting from the bit slices from the input can provide an approximated result of the sum of elements in the input weighted by the weights.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells stacked vertically above a semiconductor substrate. Each memory cell stores a weight. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells. In one example, each memory cell is formed using a transistor that includes a semiconductor layer to provide a horizontal channel. A gate layer (e.g., a gate stack layer) wraps around a circumference of the semiconductor layer. Wordlines apply gate voltages to the transistors. Each wordline has a respective portion that wraps around a circumference of the gate layer of each transistor.

Abstract: Systems, methods, and apparatus related to memory devices that use multi-pillar memory cells for performing multiplication and other operations. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. The memory cells are arranged in pillars of memory cells connected in series. Each memory cell uses at least one transistor from two or more different pillars. A bitline is formed overlying the pillars. The bitline is electrically connected to the pillars and accumulates output currents from the pillars when performing the matrix vector multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using logic states of memory cells. In one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. Voltage drivers apply different voltages to the memory cells during multiplication. The magnitudes of the different voltages correspond to a significance of the bit stored by the respective memory cell. One or more inputs are applied to the memory cells to multiply the inputs by the multi-bit weight. Output currents from the memory cells are summed on a common line. The sum of the output currents is used to provide at least one result from the multiplication.

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of memory cells. In one approach, memory cells in the sets are programmed so that each set stores a signed weight. Voltage drivers apply voltages to the memory cells in each set. The voltages correspond to signed inputs to multiply by the signed weights in the sets. One or more common lines (e.g., bitlines) are coupled to each set for summing output currents from the sets. A digitizer provides a signed result based on summing the output currents from the sets.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using sets each containing two memory cells. In one approach, sets organized as pairs of memory cells in a memory cell array are programmed so that each set stores a signed weight. Voltages are applied to the sets of memory cells at first and second times. The voltages represent signed inputs to be multiplied by the signed weights. Output currents from the memory cells in each set are accumulated at the first and second times in a respective common line for each set. A signed result for each set is provided based on digitizing sums of the output currents accumulated at the first and second times.

Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. In one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or ?1). Voltages that represent signed inputs (e.g., +1, 0, or ?1) are applied to the memory cells to perform the multiplication. A result from the multiplication is determined based on summing of output currents from the memory cells.