Abstract: Polarimetric transceiver front-ends and polarimetric phased array transceivers include two receive paths configured to receive signals from an antenna, each including a respective variable phase shifter. A first transmit path is connected to the variable phase shifter of one of the two receive paths and is configured to send signals to the antenna. A transmit/receive switch is configured to select between the first transmit path and the two receive paths for signals. The transmit/receive switch has an element that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

Abstract: Polarimetric transceiver front-ends and polarimetric phased array transceivers include two receive paths configured to receive signals from an antenna, each including a respective variable phase shifter. A first transmit path is connected to the variable phase shifter of one of the two receive paths and is configured to send signals to the antenna. A transmit/receive switch is configured to select between the first transmit path and the two receive paths for signals. The transmit/receive switch has an element that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: Methods for testing the resolution of an imaging device include forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size. The semiconductor devices are activated by providing an input signal. Light emissions from one or more of the activated semiconductor devices are suppressed by providing one or more select signals.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: A four-level pulse amplitude modulation receiver has a four-level pulse amplitude modulation mode and a non-return-to-zero modulation mode. First, second, and third four-level pulse amplitude modulation samplers are coupled to an input. Each of the samplers has a corresponding output in turn including a corresponding binary decision of the first, second, and third samplers. A four-level pulse amplitude modulation decoder circuit has inputs coupled to the outputs of the samplers. The four-level pulse amplitude modulation decoder circuit is active in the four-level pulse amplitude modulation mode. The receiver also includes a non-return-to-zero majority voting circuit coupled to the outputs of the samplers. The non-return-to-zero majority voting circuit has an output and is configured to output a majority decision of the corresponding binary decisions of the samplers, and is active in the non-return-to-zero modulation mode.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: Methods for testing the resolution of an imaging device include forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size. The semiconductor devices are activated by providing an input signal. Light emissions from one or more of the activated semiconductor devices are suppressed by providing one or more select signals.

Abstract: Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.

Abstract: Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.

Abstract: Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error.

Abstract: Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements.

Abstract: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.