Patents by Inventor Hervé Le-Gall
Hervé Le-Gall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9098426Abstract: A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.Type: GrantFiled: March 20, 2013Date of Patent: August 4, 2015Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventor: Herve Le-Gall
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Method and device for estimating parameters of a system for spreading the spectrum of a clock signal
Patent number: 8995496Abstract: A method to estimate parameters of a system to spread a spectrum of a first periodic signal according to a modulation period. An embodiment comprises sampling the first signal using a second periodic signal, determining based on the sampling result each occurrence where the first and second signals are synchronous, incrementing a first counter at each sampling, the first counter being reset at each said occurrence, storing at each said occurrence the last value of the first counter before the resetting, providing a third periodic signal at a first level when said last value is greater than a threshold and at a second level when said last value is smaller than the threshold, and determining the modulation period based on the period of the third signal.Type: GrantFiled: April 12, 2011Date of Patent: March 31, 2015Assignee: STMicroelectronics SASInventor: Hervé Le-Gall -
Publication number: 20130304787Abstract: A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.Type: ApplicationFiled: March 20, 2013Publication date: November 14, 2013Applicant: STMicroelectronics (Grenoble 2) SASInventor: Herve Le-Gall
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Patent number: 8572447Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.Type: GrantFiled: June 6, 2011Date of Patent: October 29, 2013Assignee: STMicroelectronics (Grenoble 2) SASInventor: Hervé Le-Gall
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Patent number: 8571822Abstract: A method for testing an integrated circuit, the method including performing a series of at least three tests, each including: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken.Type: GrantFiled: November 18, 2010Date of Patent: October 29, 2013Assignee: STMicroelectronics (Grenoble 2) SASInventor: Herve Le-Gall
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Publication number: 20130070830Abstract: A method for characterizing jitter of an internal clock signal of a circuit may include generating a series of samples of the internal clock signal by a reference clock signal, comparing the word formed by the N most recent samples of the series to an N-bit pattern, where N is an integer greater than, or equal to 2, and incrementing a first counter if the word complies with the pattern. The method may also include incrementing a second counter when the count of the first counter reaches a first threshold X1, and incrementing a third counter when the count of the first counter reaches a second threshold different from the first. The method may include calculating an average p and a standard deviation ? of a Gaussian density curve as a function of the counts reached in the second and third counters.Type: ApplicationFiled: September 13, 2012Publication date: March 21, 2013Applicant: STMicroelectronics (Grenoble2) SASInventor: Herve LE-GALL
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Publication number: 20110302471Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.Type: ApplicationFiled: June 6, 2011Publication date: December 8, 2011Applicant: STMicroelectronics (Grenoble 2) SASInventor: Hervé Le-Gall
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Publication number: 20110299581Abstract: A method of generating at least one test sequence for testing a data connection, the method involving selectively combining by a logic function (206) the output sequences of a plurality of pseudo-random bit sequence (PRBS) generators (202, 204), each generator having a specific number of states that is different from those of the other generators.Type: ApplicationFiled: June 6, 2011Publication date: December 8, 2011Applicant: STMicroelectronics (Grenoble 2) SASInventor: Hervé Le-Gall
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METHOD AND DEVICE FOR ESTIMATING PARAMETERS OF A SYSTEM FOR SPREADING THE SPECTRUM OF A CLOCK SIGNAL
Publication number: 20110249702Abstract: A method to estimate parameters of a system to spread a spectrum of a first periodic signal according to a modulation period. An embodiment comprises sampling the first signal using a second periodic signal, determining based on the sampling result each occurrence where the first and second signals are synchronous, incrementing a first counter at each sampling, the first counter being reset at each said occurrence, storing at each said occurrence the last value of the first counter before the resetting, providing a third periodic signal at a first level when said last value is greater than a threshold and at a second level when said last value is smaller than the threshold, and determining the modulation period based on the period of the third signal.Type: ApplicationFiled: April 12, 2011Publication date: October 13, 2011Applicant: STMICROELECTRONICS (GRENOBLE) SASInventor: Herve Le-Gall -
Publication number: 20110125437Abstract: A method for testing an integrated circuit, comprising performing a series of at least three tests, each comprising: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken.Type: ApplicationFiled: November 18, 2010Publication date: May 26, 2011Applicant: STMicroelectronics (Grenoble 2) SASInventor: Herve Le-Gall
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Patent number: 7941738Abstract: A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.Type: GrantFiled: March 9, 2007Date of Patent: May 10, 2011Assignee: STMicroelectronics S.A.Inventors: Hervé Le-Gall, Paul Armagnat, Jean-Christophe Pont
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Patent number: 7487055Abstract: A method and a device for estimating the jitter of a first periodic signal with respect to a second periodic signal, comprising steps of: sampling the first signal by means of the second one; providing the result of the sampling to the input of a shift register triggered by the second signal; comparing at least the first two states and the last state of a current word formed from parallel outputs of the shift register with respect to a reference word; and counting the number of occurrences of the reference word within a given measurement period.Type: GrantFiled: March 27, 2007Date of Patent: February 3, 2009Assignee: STMicroelectronics SAInventor: Hervé Le-Gall
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Publication number: 20070229326Abstract: A method and a device for estimating the jitter of a first periodic signal with respect to a second periodic signal, comprising steps of: sampling the first signal by means of the second one; providing the result of the sampling to the input of a shift register triggered by the second signal; comparing at least the first two states and the last state of a current word formed from parallel outputs of the shift register with respect to a reference word; and counting the number of occurrences of the reference word within a given measurement period.Type: ApplicationFiled: March 27, 2007Publication date: October 4, 2007Applicant: ST Microelectronics S.A.Inventor: Herve Le-Gall
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Publication number: 20070226595Abstract: A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.Type: ApplicationFiled: March 9, 2007Publication date: September 27, 2007Applicant: STMicroelectronics S.A.Inventors: Herve Le-Gall, Paul Armagnat, Jean-Christophe Pont