Abstract: Cancellation of a leaked transmission signal received together with a received signal is cancelled at a receiver amplifier in a system made up of the receiver amplifier, a power amplifier, and a duplexer that couples both to an antenna. A portion of the amplified transmission signal from the power amplifier is split off prior to the duplexer. That portion is controllably applied to the receiver amplifier. A feedback loop monitors the amplified output of the receiver amplifier and varies the gain and phase of the portion of the amplified transmission signal in order to minimize the amount of transmission signal in the amplified output of the receiver amplifier.

Abstract: A signal cancelling duplexer is provided. Duplexers of the invention add equal amounts of a transmission signal and an out-of-phase component of the same transmission signal at the receiver, so that both signals cancel. Duplexers of the invention can be switched between multiple channels by changing switch settings within the duplexer. RF transceivers including a power amplifier, receiver amplifier, and the signal cancelling duplexer are also provided.

Abstract: An RF circuit for wireless devices comprises a single differential power amplifier and an impedance balancing circuit for each frequency band. The impedance balancing circuit serves both to provide an appropriate impedance at the output of the amplifier as the operating mode of the device changes, and also transforms the differential output of the amplifier to a single-ended output. The impedance balancing circuit optionally comprises a BALUN circuit and a variable capacitor that is varied as the operating mode changes in order to vary the impedance at the output of the amplifier.

Abstract: An RF circuit for wireless devices comprises a single differential power amplifier and an impedance balancing circuit for each frequency band. The impedance balancing circuit serves both to provide an appropriate impedance at the output of the amplifier as the operating mode of the device changes, and also transforms the differential output of the amplifier to a single-ended output. The impedance balancing circuit optionally comprises a BALUN circuit and a variable capacitor that is varied as the operating mode changes in order to vary the impedance at the output of the amplifier.

Abstract: Switches comprising a number of transistors in series achieve improved performance through biasing the bodies of the transistors to lower the stack resistance in the ON mode and optionally to also lower the stack capacitance in the OFF mode. These switches find use in RF applications such as phase shifters, step attenuators, and in antenna switches, for example. In some embodiments, a bias network is used to alternatingly provide a positive bias voltage or a negative bias voltage to the bodies of the transistors.

Abstract: Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.

Abstract: Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.