Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.

Abstract: A system on chip (SoC) includes a system clock device configured to generate at least one system clock signal, a first area with a central processing unit and a second area with a direct memory access (DMA) circuit, a peripheral coupled to the DMA circuit, and a memory containing peripheral configuration descriptor(s) executable by the DMA circuit. In a first mode of SoC operation, the system clock device delivers the system clock signal to all areas. In a second mode of SoC operation, the system clock device does not deliver the system clock signal to any area. In a third mode of SoC operation, the system clock device distributes the system clock signal to a part of the second area without delivering the system clock signal to the other areas and the DMA circuit configures the peripheral in response to the execution of the configuration descriptor(s).

Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.

Abstract: A decoding circuit and associated method are provided for decoding a biphase signal. The decoding circuit may include a precharging register to precharge a pair of states of the biphase signal, where a state of the pair of states is precharged at each pulse of a periodic precharging signal. The decoding circuit may further include a verification circuit to compare the two states of the pair of states and give an active error signal if the two states are equal.

Abstract: A decoding circuit and associated method are provided for decoding a biphase signal. The decoding circuit may include a precharging register to precharge a pair of states of the biphase signal, where a state of the pair of states is precharged at each pulse of a periodic precharging signal. The decoding circuit may further include a verification circuit to compare the two states of the pair of states and give an active error signal if the two states are equal.