Abstract: A signal processing circuit is proposed, which is intended to receive a pair of input signals Sp and Sn in phase opposition on two input terminals and to provide two pairs of output currents SIp and SIn in phase opposition on four output terminals. Each input signal Sp and Sn is amplified in an amplification unit LNAUp and LNAUn and subsequently split in a splitting unit SPLUp and SPLUn. The invention is such that each of the two splitting units SPLUp and SPLUn includes at least two branches, respectively BIp, BQp and BIn, BQn connected between said amplification unit, respectively LNAUp and LNAUn, and one of said output terminals, the four branches BIp, BQp and BIn and BQn each including at least an impedance, respectively RIp, RQp, RIn, RQn, having identical characteristics. Mixer circuits can be easily stacked with this signal processing circuit.

Abstract: A signal processing circuit is proposed, which is intended to receive a pair of input signals Sp and Sn in phase opposition on two input terminals and to provide two pairs of output currents SIp and SIn in phase opposition on four output terminals. Each input signal Sp and Sn is amplified in an amplification unit LNAUp and LNAUn and subsequently split in a splitting unit SPLUp and SPLUn. The invention is such that each of the two splitting units SPLUp and SPLUn includes at least two branches, respectively BIp, BQp and BIn, BQn connected between said amplification unit, respectively LNAUp and LNAUn, and one of said output terminals, the four branches BIp, BQp and BIn and BQn each including at least an impedance, respectively RIp, RQp, RIn, RQn, having identical characteristics. Mixer circuits can be easily stacked with this signal processing circuit.

Abstract: What is involved is a transconductance circuit is discussed, having at least one transconductance subcircuit (100) that is connected between two supply terminals (20, 21) and includes at least one MOS transistor (M1, M1′). It comprises means (200) for biasing the MOS transistor (M1, M1′) in the subcircuit (100) with a biasing current whose variation as a function of temperature substantially compensates for that of the mobility of the majority carriers in the channel of the MOS transistor (M1, M1′) in the subcircuit (100), in such a way as to make the transconductance of the circuit substantially independent of temperature.

Abstract: The invention relates to a reference voltage generator which comprises, arranged between two supply terminals (20, 21), an input stage (1) having a portion (R0) proportional to the absolute temperature and delivering a potential which is substantially independent of temperature, connected to an operational amplifier (2) which delivers the reference voltage (Vref) and is fed back to the input stage. The components of the operational amplifier (2) are chosen so that even in an open loop arrangement (3) the reference voltage is substantially independent of the supply voltage, and the manufacturing method and has a given dependence on temperature.

Abstract: The invention relates to a reference voltage generator which comprises, arranged between two supply terminals (20, 21), an input stage (1) having a portion (R0) proportional to the absolute temperature and delivering a potential which is substantially independent of temperature, connected to an operational amplifier (2) which delivers the reference voltage (Vref) and is fed back to the input stage. The components of the operational amplifier (2) are chosen so that even in an open loop arrangement (3) the reference voltage is substantially independent of the supply voltage, and the manufacturing method and has a given dependence on temperature.

Abstract: What is involved is a transconductance circuit is discussed, having at least one transconductance subcircuit (100) that is connected between two supply terminals (20, 21) and includes at least one MOS transistor (M1, M1′). It comprises means (200) for biasing the MOS transistor (M1, M1′) in the subcircuit (100) with a biasing current whose variation as a function of temperature substantially compensates for that of the mobility of the majority carriers in the channel of the MOS transistor (M1, M1′) in the subcircuit (100), in such a way as to make the transconductance of the circuit substantially independent of temperature.