Patents by Inventor Herve Letourneur

Herve Letourneur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8825925
    Abstract: An example method and system process a SuperSpeed packet transferred at a SuperSpeed transfer rate and based on processing the SuperSpeed packet, generate a Universal Serial Bus (USB) 2.0 packet to be transferred at a USB 2.0 transfer rate, the USB 2.0 transfer rate being less than the SuperSpeed transfer rate.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 2, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gaurav Singh, Herve LeTourneur, Hans Van Antwerpen, Cathal G. Phelan
  • Patent number: 8645598
    Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 4, 2014
    Assignee: Cypress Semiconductor Corp.
    Inventors: Hans Van Antwerpen, Herve Letourneur
  • Publication number: 20130145056
    Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.
    Type: Application
    Filed: September 14, 2012
    Publication date: June 6, 2013
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Hans Van Antwerpen, Herve Letourneur
  • Patent number: 8447890
    Abstract: A multiple master USB hub device and method for enabling multiple OTG and host devices to control peripherals and slave devices with a connection of the multiple OTG and host devices to the USB hub device. The multiple master USB hub device is configured to enable at least two USB devices connected thereto to each be configured as host/master elements to control OTG and peripheral/slave devices connected to the USB hub device, the USB hub device comprising an element configured to switch configuration of each of the at least two USB devices to a host/master configuration at different predetermined times.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: May 21, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Herve LeTourneur, Hans Van Antwerpen
  • Patent number: 8364870
    Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: January 29, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hans Van Antwerpen, Herve Letourneur
  • Publication number: 20120084470
    Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.
    Type: Application
    Filed: March 31, 2011
    Publication date: April 5, 2012
    Applicant: Cypress Semiconductor Corporation
    Inventors: Hans Van Antwerpen, Herve Letourneur
  • Patent number: 8112571
    Abstract: A device may include a first data path coupled between a first port and a data transfer section that enables data paths between the first data path and at least a second port and a third port. A second data path may be coupled between the first port and the second port that bypasses the data transfer section and is not coupled to the second or third ports.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: February 7, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Herve Letourneur
  • Patent number: 8060708
    Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 15, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Dinesh Maheshwari, Dinesh Ramanathan, Alakesh Chetia, Herve Letourneur, Donald W. Smith, Manoj Gujral
  • Publication number: 20100312952
    Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Dinesh Maheshwari, Dinesh Ramanathan, Alakesh Chetia, Hervé Letourneur, Donald W. Smith, Manoj Gujral
  • Patent number: 7730268
    Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: June 1, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Dinesh Maheshwari, Dinesh Ramanathan, Alakesh Chetia, Hervé Letourneur, Donald W. Smith, Manoj Gujral
  • Publication number: 20080046638
    Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.
    Type: Application
    Filed: August 18, 2006
    Publication date: February 21, 2008
    Applicant: CYPRESS SEMICONDUCTOR CORP.
    Inventors: Dinesh Maheshwari, Dinesh Ramanathan, Alakesh Chetia, Herve Letourneur, Donald W. Smith, Manoj Gujral