Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to generate usage dependent code embeddings. An example apparatus includes parsing circuitry to select a usage context of a code snippet including at least one line of code (LOC) before the code snippet or an LOC at which the code snippet is called, the code snippet, and at least one LOC after the code snippet or the LOC. The example apparatus additionally includes embedding circuitry to generate a first list of token embedding vectors for first tokens of a second list of tokens for the code snippet and a third list of token embedding vectors for second tokens of a fourth list of tokens for the usage context. The example apparatus also includes concatenation circuitry to concatenate a transformed token embedding vector of a close token and a fifth list of transformed token embedding vectors for the first list.

Abstract: The apparatus of an edge computing node, a system, a method and a machine-readable medium. The apparatus includes a processor to cause an initial set of weights for a global machine learning (ML) model to be transmitted a set of client compute nodes of the edge computing network; process Hessians computed by each of the client compute nodes based on a dataset stored on the client compute node; evaluate a gradient expression for the ML model based on a second dataset and an updated set of weights received from the client compute nodes; and generate a meta-updated set of weights for the global model based on the initial set of weights, the Hessians received, and the evaluated gradient expression.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to train a machine learning model. An example apparatus to generate adaptive hyper-parameters includes a model aggregator to, in response to obtaining at least one model trained using a first set of hyper-parameters of a probability distribution, generate a loss reduction, a hyper-parameter generator to, when the loss reduction satisfies a loss threshold, update the probability distribution and generate a second set of hyper-parameters using the updated probability distribution, and an interface to transmit the second set of hyper-parameters to a client.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to generate usage dependent code embeddings. An example apparatus includes parsing circuitry to select a usage context of a code snippet including at least one line of code (LOC) before the code snippet or an LOC at which the code snippet is called, the code snippet, and at least one LOC after the code snippet or the LOC. The example apparatus additionally includes embedding circuitry to generate a first list of token embedding vectors for first tokens of a second list of tokens for the code snippet and a third list of token embedding vectors for second tokens of a fourth list of tokens for the usage context. The example apparatus also includes concatenation circuitry to concatenate a transformed token embedding vector of a close token and a fifth list of transformed token embedding vectors for the first list.

Abstract: Various embodiments provide apparatuses, systems, and methods related to a first worker of a distributed neural network (NN), The first worker may execute a forward training pass of a first node of a distributed NN, wherein execution of the forward training pass includes generation of a first computational graph (CG) that is based on inputs related to a second node that is processed by a second worker of the distributed NN. The first worker may also delete, subsequent to the forward training pass of the first node, the CG. The first worker may also execute, a backward pass of the first node, wherein execution of the backward pass includes re-generation of at least a portion of the first CG. Other embodiments may be described and claimed.

Abstract: A compute-in-memory neural network architecture combines neural circuits implemented in CMOS technology and synaptic conductance crossbar arrays. The crossbar memory structures store the weight parameters of the neural network in the conductances of the synapse elements, which define interconnects between lines of neurons of consecutive layers in the network at the crossbar intersection points.

Abstract: Methods, systems, and computer programs are presented for implementing Personalized Mobility as a Service (PMaaS) to improve transportation services delivery. One storage medium includes instructions for detecting, by a mobility as a service (MaaS) system, a request for a trip from a user device of a user. The storage medium further includes instructions for mapping, using a model executing on the machine, the user to a persona from a plurality of persona models. Each persona model has one or more characteristics associated with users of the MaaS system. Further yet, the storage medium includes instructions for determining trip parameters for the trip based on the persona mapped to the user, the trip parameters defining one or more trip segments for the trip, and instructions for providing trip parameters to the user device.

Abstract: A method includes receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit. The method includes determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit, determining first gain coefficients and second gain coefficients for a filter of the PLL circuit, and determining ratio values for a divider circuit of the PLL circuit based on the data. The method includes providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration. The method includes subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO, and providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

Abstract: During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.

Abstract: A phase lock loop circuit includes a phase frequency detector, a voltage controlled oscillator, a phase interpolator, a clock signal selector, a selection module, a multiplexer, and a divider. The phase frequency detector compares phases of a reference clock and frequency divided output signals and generates an error signal. The voltage controlled oscillator, based on the error signal, generates a phase lock loop output signal and output clock signals. The phase interpolator phase interpolates the output clock signals to generate an interpolator output signal. The clock signal selector selects one of the output clock signals. The selection module generates a selection signal based on states of the interpolator output and selected output clock signals. The multiplexer, based on the selection signal, selects the interpolator output signal or the selected output clock signal. The divider frequency divides an output of the multiplexer to provide the frequency divided output signal.

Abstract: A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.

Abstract: In some implementations, a system includes a phase locked loop (PLL) circuit and a digital control unit. The PLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), and a divider circuit. The digital control unit is configured determine a preset value for the DCO; determine initial gain coefficients and final gain coefficients for the digital loop filter; determine N/R values for the divider circuit; while the PLL circuit is operating in an open-loop configuration, provide the preset value to the DCO, the initial gain coefficients to the digital loop filter, and the N/R values to the divider circuit; after providing the preset value, initial gain coefficients, and N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the final gain coefficients to the digital loop filter.

Abstract: A convolution processing apparatus and method are disclosed. The convolution processing apparatus may include a controller configured to load a pixel of an input image and skip a process associated with the pixel in response to a value of the loaded pixel being 0, a filter bank including at least one filter and configured to extract at least one kernel element corresponding to the pixel from the at least one filter based on an index of the pixel and an input channel of the pixel, and a multiplier-accumulator (MAC) configured to perform a convolution operation based on the value of the pixel and a value of the at least one kernel element and accumulatively store an operation result of the convolution operation, the operation result corresponding to an output image.

Abstract: The present disclosure describes variable gain amplifiers with gain-based compensation. In some embodiments, a variable gain amplifier (VGA) includes a gain stage, an output stage, a compensation stage, and a capacitor coupled between respective outputs of the gain stage and compensation stage. A gain of the VGA is configured, based on a gain setting, to amplify signals received by the variable gain amplifier. A gain of the compensation stage is configured, based on the gain setting, to alter an effective capacitance of the capacitor, which is applied to the output of the gain stage for compensation of the VGA. By altering the effective capacitance based on the gain setting of the VGA, compensation capacitance is adjusted continuously with changes in the gain setting and at a similar resolution. In various embodiments, the continuous adjustment of the compensation capacitance across different gain levels prevents discontinuities in amplifier compensation.

Abstract: A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.

Abstract: In some implementations, a system includes a magnetic media disk and a read/write unit. The read/write unit includes a plurality of phase-locked loops (PLLs), an interpolator unit, a delay-locked loop, and a precompensation unit. The PLLs are configured to generate, using a reference clock signal, a first plurality of clock signals having different frequencies phases. The interpolator unit is configured to interpolate the first plurality of clock signals in accordance with a frequency offset signal to generate a single-phase clock signal. The delay-locked loop is configured to delay the single-phase clock signal in accordance with a PLL data clock signal to generate a second plurality of clock signals having different phases. The precompensation unit is configured to apply precompensation to the second plurality of clock signals to generate a timing signal for writing data to the magnetic media disk.

Abstract: A precompensation circuit can include: a rising edge interpolator circuit configured to generate a phase shifted rising edge data signal; a falling edge interpolator circuit configured to generate a phase shifted falling edge data signal; a multiplexer circuit coupled with the rising edge interpolator circuit and with the falling edge interpolator circuit to multiplex the phase shifted rising edge data signal and the phase shifted falling edge data signal into an output data signal responsive to a select signal; and a control circuit coupled with the select input of the multiplexer circuit to control production of the output data signal, wherein the control circuit is further coupled with both the rising edge interpolator circuit and the falling edge interpolator circuit to change the select signal to the multiplexer circuit at times determined by both the phase shifted rising edge data signal and the phase shifted falling edge data signal.

Abstract: A convolution processing apparatus and method are disclosed. The convolution processing apparatus may include a controller configured to load a pixel of an input image and skip a process associated with the pixel in response to a value of the loaded pixel being 0, a filter bank including at least one filter and configured to extract at least one kernel element corresponding to the pixel from the at least one filter based on an index of the pixel and an input channel of the pixel, and a multiplier-accumulator (MAC) configured to perform a convolution operation based on the value of the pixel and a value of the at least one kernel element and accumulatively store an operation result of the convolution operation, the operation result corresponding to an output image.