Abstract: A driver configuration for driving a Mach-Zehnder modulator (MZM) includes a first driver supplied by a first voltage and a second voltage and configured to provide a first two complimentary outputs respectively to a first N-electrode of a first branch of the MZM and a second N-electrode of a second branch of the MZM. Additionally, the driver configuration includes a second driver supplied by a third voltage and a fourth voltage and configured to provide a second two complimentary outputs respectively to a first P-electrode of the first branch and a second P-electrode of the second branch. The driver configuration sets a difference between the third voltage and the fourth voltage equal to a difference between the first voltage and the second voltage to provide a same peak-to-peak differential swing for modulating light wave through each transmission line and output a modulated light with twice of the peak-to-peak differential swing.

Abstract: A driver configuration for driving a Mach-Zehnder modulator (MZM) includes a first driver supplied by a first voltage and a second voltage and configured to provide a first two complimentary outputs respectively to a first N-electrode of a first branch of the MZM and a second N-electrode of a second branch of the MZM. Additionally, the driver configuration includes a second driver supplied by a third voltage and a fourth voltage and configured to provide a second two complimentary outputs respectively to a first P-electrode of the first branch and a second P-electrode of the second branch. The driver configuration sets a difference between the third voltage and the fourth voltage equal to a difference between the first voltage and the second voltage to provide a same peak-to-peak differential swing for modulating light wave through each transmission line and output a modulated light with twice of the peak-to-peak differential swing.

Abstract: A driver configuration for driving a Mach-Zehnder modulator (MZM) includes a first driver supplied by a first voltage and a second voltage and configured to provide a first two complimentary outputs respectively to a first N-electrode of a first branch of the MZM and a second N-electrode of a second branch of the MZM. Additionally, the driver configuration includes a second driver supplied by a third voltage and a fourth voltage and configured to provide a second two complimentary outputs respectively to a first P-electrode of the first branch and a second P-electrode of the second branch. The driver configuration sets a difference between the third voltage and the fourth voltage equal to a difference between the first voltage and the second voltage to provide a same peak-to-peak differential swing for modulating light wave through each transmission line and output a modulated light with twice of the peak-to-peak differential swing.

Abstract: A driver configuration for driving a Mach-Zehnder modulator (MZM) includes a first driver supplied by a first voltage and a second voltage and configured to provide a first two complimentary outputs respectively to a first N-electrode of a first branch of the MZM and a second N-electrode of a second branch of the MZM. Additionally, the driver configuration includes a second driver supplied by a third voltage and a fourth voltage and configured to provide a second two complimentary outputs respectively to a first P-electrode of the first branch and a second P-electrode of the second branch. The driver configuration sets a difference between the third voltage and the fourth voltage equal to a difference between the first voltage and the second voltage to provide a same peak-to-peak differential swing for modulating light wave through each transmission line and output a modulated light with twice of the peak-to-peak differential swing.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: An apparatus comprising an input, a control signal generator coupled to the input and having a control signal generator output, and an amplifier coupled to the control signal generator output, wherein a voltage supplied to the amplifier is switched based on the control signal generator output, and wherein the control signal generator output is based on a data signal in the input. Also included is an apparatus comprising circuitry configured to implement a method comprising detecting an incoming signal, calculating a derivative of the incoming signal, estimating a future incoming signal based on the derivative of the incoming signal and a time step, and providing the estimated future incoming signal to switch between a first supply voltage and a second supply voltage prior to or concurrent with an arrival of the future incoming signal at the switch, wherein the incoming signal and the future incoming signal are analog signals.

Abstract: The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Abstract: An apparatus comprising an input, a control signal generator coupled to the input and having a control signal generator output, and an amplifier coupled to the control signal generator output, wherein a voltage supplied to the amplifier is switched based on the control signal generator output, and wherein the control signal generator output is based on a data signal in the input. Also included is an apparatus comprising circuitry configured to implement a method comprising detecting an incoming signal, calculating a derivative of the incoming signal, estimating a future incoming signal based on the derivative of the incoming signal and a time step, and providing the estimated future incoming signal to switch between a first supply voltage and a second supply voltage prior to or concurrent with an arrival of the future incoming signal at the switch, wherein the incoming signal and the future incoming signal are analog signals.

Abstract: A splitterless interface between a digital subscriber line (DSL) and the central office equipment that can receive and isolate the low frequency voice data and high frequency digital data from a telephone line. This interface can also mix and transmit low frequency voice data and high frequency digital data onto a telephone line. For POTS band frequencies, a reactive impedance coupled across the two-wire interface of the POTS line card, and serially coupled to the line side of the DSL coupling transformer, has an open state magnitude. The magnitude of the line side windings of the DSL coupling transformer is low at POTS band frequencies. POTS band signal power is therefore delivered to the POTS line card. For DSL band frequencies, the reactive impedance across the two-wire interface of the POTS line card has a closed state magnitude. The POTS line card is therefore essentially short-circuited at DSL band frequencies, and DSL band signal power is delivered to the DSL modem.

Abstract: An apparatus and method to implement a highly efficient low power line driver. In a first embodiment, the invention provides a method to increase the power efficiency of a line driver. The method includes supplying a digital signal processor output to a first subtractor; supplying the first subtractor output as an input to a modulator of a line driver; subtracting the line driver output from the digital signal processor output at the first subtractor; filtering the line driver output with a low pass filter; routing the line driver output to an impedance match filter; providing a first analog-to-digital converter and a second subtractor to subtract the line impedance match filter output from the low pass filter output; providing a digital filter and a second analog-to-digital converter; and subtracting the digital filter output from the first analog-to-digital converter output at a third subtractor to output a feedback signal to the digital signal processor.

Abstract: An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2B to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage.

Abstract: A transformerless data access arrangement (DAA) device facilitates data transfer between a high speed modem device and a central office telephone line (i.e., a phone line). The DAA device uses D/A and A/D converters in conjunction with a pair of nonlinear opto-couplers that function as an isolation barrier. The A/D converter converts an analog signal received from the phone line into a one-bit modulated digital signal. The digital signal is relayed by the nonlinear opto-couplers to a processor. Since the relayed signal is digital, the use of nonlinear opto-couplers does not result in unacceptable levels of noise and distortion. This is relevant since high speed modems have stringent noise and distortion requirements. A phone line supply voltage is regulated internally and used to power the DAA device. When the processor detects a ring signal on the phone line, the processor generates a control signal which places the A/D and D/A converters in idle mode while sending a caller ID directly to the processor.