Patents by Inventor Hetansh Pareshbhai Shah

Hetansh Pareshbhai Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits and methods for capacitor modulation
    Patent number: 11574660
    Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 7, 2023
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Nimish Sharma, Hetansh Pareshbhai Shah, Bo Zheng
  • Circuits and Methods for Capacitor Modulation
    Publication number: 20220051704
    Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 17, 2022
    Inventors: Lalit Gupta, Nimish Sharma, Hetansh Pareshbhai Shah, Bo Zheng
  • Write Assist Circuitry
    Publication number: 20210158865
    Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Inventors: Lalit Gupta, El Mehdi Boujamaa, Nicolaas Klarinus Johannes VAN WINKELHOFF, Bo Zheng, Fakhruddin Ali Bohra, Nimish Sharma, Hetansh Pareshbhai Shah
  • Write assist circuitry
    Patent number: 11004503
    Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 11, 2021
    Assignee: Arm Limited
    Inventors: Lalit Gupta, El Mehdi Boujamaa, Nicolaas Klarinus Johannes Van Winkelhoff, Bo Zheng, Fakhruddin Ali Bohra, Nimish Sharma, Hetansh Pareshbhai Shah