Patents by Inventor Heui-Won Shin

Heui-Won Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same
    Publication number: 20070114635
    Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.
    Type: Application
    Filed: January 9, 2007
    Publication date: May 24, 2007
    Inventors: Tai-Heui Cho, Hyuck-Jin Kang, Heui-Won Shin, Gwang-Seon Byun, Sun-Joon Kim
  • Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same
    Patent number: 7180154
    Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-Heui Cho, Hyuck-Jin Kang, Heui-Won Shin, Gwang-Seon Byun, Sun-Joon Kim
  • Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same
    Publication number: 20040262768
    Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.
    Type: Application
    Filed: May 13, 2004
    Publication date: December 30, 2004
    Inventors: Tai-Heui Cho, Hyuck-Jin Kang, Heui-Won Shin, Gwang-Seon Byun, Sun-Joon Kim