Patents by Inventor Heung Lak Park
Heung Lak Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8563095Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.Type: GrantFiled: March 15, 2010Date of Patent: October 22, 2013Assignee: Applied Materials, Inc.Inventors: Nagarajan Rajagopalan, Xinhai Han, Ryan Yamase, Ji Ae Park, Shamik Patel, Thomas Nowak, Zhengjiang “David” Cui, Mehul Naik, Heung Lak Park, Ran Ding, Bok Hoen Kim
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Publication number: 20130161629Abstract: Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550° C.; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600° C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700° C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods.Type: ApplicationFiled: December 27, 2011Publication date: June 27, 2013Applicant: APPLIED MATERIALS, INC.Inventors: XINHAI HAN, NAGARAJAN RAJAGOPALAN, GUANGCHI XUAN, JIANHUA ZHOU, JIGANG LI, SHAHID SHAIKH, PATRICK REILLY, THOMAS NOWAK, JUAN CARLOS ROCHA-ALVAREZ, HEUNG LAK PARK, BOK HOEN KIM
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Patent number: 8349741Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less, and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater.Type: GrantFiled: April 25, 2012Date of Patent: January 8, 2013Assignee: Applied Materials, Inc.Inventors: Hang Yu, Deenesh Padhi, Man-Ping Cai, Naomi Yoshida, Li Yan Miao, Siu F. Cheng, Shahid Shaikh, Sohyun Park, Heung Lak Park, Bok Hoen Kim
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Patent number: 8298887Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.Type: GrantFiled: June 25, 2010Date of Patent: October 30, 2012Assignee: Applied Materials, Inc.Inventors: Xinhai Han, Nagarajan Rajagopalan, Ji Ae Park, Bencherki Mebarki, Heung Lak Park, Bok Hoen Kim
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Publication number: 20120208374Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less, and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater.Type: ApplicationFiled: April 25, 2012Publication date: August 16, 2012Applicant: Applied Materials, Inc.Inventors: Hang Yu, Deenesh Padhi, Man-Ping Cai, Naomi Yoshida, Li Yan Miao, Siu F. Cheng, Shahid Shaikh, Sohyun Park, Heung Lak Park, Bok Hoen Kim
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Patent number: 8227352Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer.Type: GrantFiled: April 25, 2011Date of Patent: July 24, 2012Assignee: Applied Materials, Inc.Inventors: Hang Yu, Deenesh Padhi, Man-Ping Cai, Naomi Yoshida, Li Yan Miao, Siu F. Cheng, Shahid Shaikh, Sohyun Park, Heung Lak Park, Bok Hoen Kim
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Publication number: 20120043518Abstract: An electronic device comprises a variable resistance memory element on a substrate. The variable resistance memory element comprises (i) an amorphous carbon layer comprising a hydrogen content of at least about 30 atomic percent, and a maximum leakage current of less than about 1×10?9 amps, and (ii) a pair of electrodes about the amorphous carbon layer. Methods of fabricating this and other devices are also described.Type: ApplicationFiled: August 18, 2010Publication date: February 23, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Siu F. CHENG, Heung Lak PARK, Deenesh PADHI
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Publication number: 20120015521Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer.Type: ApplicationFiled: April 25, 2011Publication date: January 19, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Hang Yu, Deenesh Padhi, Man-Ping Cai, Naomi Yoshida, Li Yan Miao, Siu F. Cheng, Shahid Shaikh, Sohyun Park, Heung Lak Park, Bok Hoen Kim
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Publication number: 20110223765Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.Type: ApplicationFiled: March 15, 2010Publication date: September 15, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Ryan YAMASE, Ji Ae PARK, Shamik PATEL, Thomas NOWAK, Zhengjiang "David" CUI, Mehul NAIK, Heung Lak PARK, Ran DING, Bok Hoen KIM
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Publication number: 20110136327Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.Type: ApplicationFiled: June 25, 2010Publication date: June 9, 2011Applicant: Applied Materials, Inc.Inventors: Xinhai Han, Nagarajan Rajagopalan, Ji Ae Park, Bencherki Mebarki, Heung Lak Park, Bok Hoen Kim
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Publication number: 20040065540Abstract: A treating head having a treating surface and a substrate treatment surface define a thin fluid gap that is filled with reactant liquid to form a thin liquid layer on the substrate for conducting a liquid chemical reaction treatment or other liquid treatment of the substrate. The thin liquid layer has a volume in a range of about from 50 ml to 500 ml. Preferably, the chemical composition, temperature, and other properties of liquid in the thin liquid layer are dynamically variable.Type: ApplicationFiled: June 30, 2003Publication date: April 8, 2004Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, Jonathan D. Reid, Timothy Patrick Cleary, Edmund B. Minshall, R. Marshall Stowell, Heung Lak Park
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Patent number: 5918142Abstract: A method for fabricating a semiconductor device, wherein, when a blanket of the planarization layer is deposited and thermally treated for its reflow after the formation of a metal gate electrode consisting of a CVD-TiN layer pattern and a W layer pattern on a semiconductor substrate, a gate oxide is formed at the interface between the CVD-TiN layer and the semiconductor substrate by the reaction of the moisture absorbed in the CVD-TiN layer with the Si of the substrate, without executing an additional process and, thus, the stress between the gate oxide and the metal layer is not high, so that the gate oxide can be prevented from being degraded, and the production yield and the reliability of device operation is improved.Type: GrantFiled: June 26, 1997Date of Patent: June 29, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Heung Lak Park, Sang Hyeob Lee
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Patent number: 5739049Abstract: A method for fabricating a semiconductor device having a capacitor exhibiting improved insulating and ferroelectric characteristics. The method involves forming a lower insulating layer over a semiconductor substrate, selectively removing the lower insulating layer to form a contact hole, forming a ruthenium film over the lower insulating layer, selectively removing the ruthenium film, thereby forming a lower electrode, and forming a ruthenium oxide film over the lower electrode. A method for forming a metal wiring is also provided.Type: GrantFiled: August 19, 1996Date of Patent: April 14, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Heung Lak Park, Kyeong Keun Choi