Patents by Inventor Heung-Mook Kim

Heung-Mook Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11632136
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 18, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11616864
    Abstract: An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing time interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: March 28, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae-Young Lee, Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Heung-Mook Kim
  • Patent number: 11616600
    Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time -interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and a boundary between the time interleaver groups is a boundary between Physical Layer Pipes (PLPs) of a core layer corresponding to the core layer signal.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 28, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sun-Hyoung Kwon, Jae-Young Lee, Sung-Ik Park, Bo-Mi Lim, Heung-Mook Kim, Jin-Hyuk Song
  • Patent number: 11611357
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: March 21, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11606168
    Abstract: An apparatus and method for transmitting broadcast signal to which channel bonding is applied are disclosed. The apparatus according to the present invention includes an input formatting unit configured to generate baseband packets corresponding to a plurality of packet types using data corresponding to a physical layer pipe; a stream partitioner configured to partition the baseband packets into a plurality of partitioned streams corresponding to the plurality of packet types; BICM units configured to perform error correction encoding, interleaving and modulation corresponding to the plurality of partitioned streams, respectively; and waveform generators configured to generate RF transmission signals corresponding to the plurality of partitioned streams, respectively.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 14, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Jae-Young Lee, Sun-Hyoung Kwon, Nam-Ho Hur, Heung-Mook Kim
  • Publication number: 20230054474
    Abstract: An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the preamble includes a field indicating a start position of a first complete FEC block corresponding to each of physical layer pipes.
    Type: Application
    Filed: April 6, 2022
    Publication date: February 23, 2023
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sun-Hyoung KWON, Sung-Ik PARK, Jae-Young LEE, Bo-Mi LIM, Heung-Mook KIM, Nam-Ho HUR
  • Patent number: 11588502
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: February 21, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11588503
    Abstract: A parity puncturing apparatus and method for variable length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 21, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
  • Patent number: 11581904
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: February 14, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11563616
    Abstract: An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: January 24, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae-Young Lee, Sun-Hyoung Kwon, Sung-Ik Park, Bo-Mi Lim, Heung-Mook Kim
  • Patent number: 11564190
    Abstract: Disclosed herein are a gateway-signaling method for frequency/timing offsets and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a frequency/timing decision unit for determining a center frequency to which a frequency offset is applied using a carrier offset, which is identified using a timing and a management packet transmitted through a Studio-to-Transmitter Link (STL); and an RF signal generation unit for generating an RF signal to be transmitted, which corresponds to the center frequency.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 24, 2023
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae-Young Lee, Sung-Ik Park, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11556418
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 17, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11539379
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: December 27, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Publication number: 20220393700
    Abstract: A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 8, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM
  • Publication number: 20220394117
    Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 8, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Bo-Mi LIM, Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR
  • Publication number: 20220394115
    Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information shared by the core layer signal and the enhanced layer signal, using the time-interleaved signal.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 8, 2022
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae-Young LEE, Heung-Mook KIM, Sung-Ik PARK, Sun-Hyoung KWON
  • Publication number: 20220393916
    Abstract: Disclosed herein are a gateway-signaling method for Multiple-Input Single-Output (MISO) operation and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a predistortion unit for performing predistortion for decorrelating signals corresponding to transmitters using the number of transmitters used for MISO and a transmitter coefficient index that are identified using a timing and management packet transmitted through a Studio-to-Transmitter Link (STL), thereby generating a pre-distorted signal; and an RF signal generation unit for generating an RF transmission signal using the pre-distorted signal corresponding to the transmitter coefficient index.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 8, 2022
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae-Young LEE, Sung-Ik PARK, Sun-Hyoung KWON, Heung-Mook KIM, Nam-Ho HUR
  • Publication number: 20220360282
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Application
    Filed: July 13, 2022
    Publication date: November 10, 2022
    Inventors: Sung-Ik PARK, Heung-Mook KIM, Sun-Hyoung KWON, Nam-Ho HUR
  • Patent number: 11496978
    Abstract: Disclosed herein are a gateway-signaling method for frequency/timing offsets and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a frequency/timing decision unit for determining a center frequency to which a frequency offset is applied using a carrier offset, which is identified using a timing and a management packet transmitted through a Studio-to-Transmitter Link (STL); and an RF signal generation unit for generating an RF signal to be transmitted, which corresponds to the center frequency.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 8, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae-Young Lee, Sung-Ik Park, Sun-Hyoung Kwon, Heung-Mook Kim, Nam-Ho Hur
  • Publication number: 20220329264
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 13, 2022
    Inventors: Sung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM, Nam-Ho HUR