Abstract: The present invention provides a method for removing residue from a cavity during the formation of an interconnect structure, a method for manufacturing an interconnect structure using the same, and a method for manufacturing an integrated circuit using the same. The method for removing residue from a cavity during the formation of an interconnect structure, among other steps, may include subjecting residue (410) having an embedded metal therein located within a cavity (310) in a dielectric layer (240) and over at least a portion of a conductive feature (220) to a short duration oxidation process so as to oxidize a substantial portion of the embedded metal, and removing the residue (410) containing the oxidized embedded metal using an etch process.

Abstract: Standard post-etch photoresist clean procedures for porous dielectric materials manufacturing may involve wet cleans in which a solvent is used for polymer residue removal. In many cases, the components of the solvent are absorbed into porous film layers and can later volatilize during subsequent metal deposition steps. A low pressure anneal of limited duration and high temperature, performed after the wet clean and prior to metal deposition, satisfactorily removes the absorbed components.

Abstract: A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer (40) formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (40), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer (40).

Abstract: A method of forming an organosilicate low dielectric constant insulating layer (40) in an integrated circuit, and an integrated circuit structure having such a low-k insulating layer (40), are disclosed. In the case where the low-k dielectric material of the insulating layer (40) comprises an organosilicate glass, subsequent plasma processing has been observed to break bonds between silicon and organic moieties, either by replacing an organic group with a hydroxyl group or with hydrogen, or by leaving a dangling bond. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a silylation agent such as hexamethyldisilazane, which reacts with the damaged molecules, and forms molecules that restore the properties of the film.

Abstract: A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer (40) formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (40), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer (40).

Abstract: Cleaning methods are disclosed for removing sidewall polymers from interconnect vias or trenches, wherein a wafer is exposed to a plasma comprising hydrogen and an inert gas in a plasma cleaning chamber following etch-stop etching.

Abstract: Cleaning methods are disclosed for removing sidewall polymers from interconnect vias or trenches, wherein a wafer is exposed to a plasma comprising hydrogen and an inert gas in a plasma cleaning chamber following etch-stop etching.

Abstract: In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.

Abstract: In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.