Patents by Inventor Heung Kyu Kwon

Heung Kyu Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10593652
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Publication number: 20190319012
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 17, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu KWON, Min-Ok NA, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Patent number: 10403606
    Abstract: A method for fabricating a semiconductor package including mounting a first semiconductor chip on a first substrate, disposing a first connector on the first substrate, placing a molding control film on the first semiconductor chip to horizontally extend over the first substrate, filling a space between the molding control film and the first substrate with a molding compound such that the molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and does not cover a top surface of the first semiconductor chip, detaching the molding control film, forming an opening through the molding compound to expose a portion of the first connector, disposing a second connector and a second semiconductor chip on opposite surfaces of a second substrate, respectively, and placing the second substrate on the first substrate such that the second connector contacts the first connector may be provided.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Publication number: 20180331071
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 15, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu KWON, Min-Ok NA, Sung-Woo PARK, Ji-Hyun PARK, Su-Min PARK
  • Patent number: 10056321
    Abstract: A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: August 21, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heung-Kyu Kwon, Jong-Kook Kim
  • Patent number: 10025354
    Abstract: A system module includes a printed circuit board (PCB), a first semiconductor chip embedded in the PCB, a semiconductor package connected to the PCB through a plurality of stack balls, and a second semiconductor chip disposed on a surface of the PCB in a space between the PCB and the semiconductor package.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Heung Kyu Kwon
  • Patent number: 9984032
    Abstract: A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heung Kyu Kwon
  • Patent number: 9978721
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Patent number: 9839127
    Abstract: A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung Kyu Kwon, Kyoung Mook Lim
  • Patent number: 9811122
    Abstract: A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heung Kyu Kwon
  • Publication number: 20170185107
    Abstract: A system module includes a printed circuit board (PCB), a first semiconductor chip embedded in the PCB, a semiconductor package connected to the PCB through a plurality of stack balls, and a second semiconductor chip disposed on a surface of the PCB in a space between the PCB and the semiconductor package.
    Type: Application
    Filed: September 20, 2016
    Publication date: June 29, 2017
    Inventor: HEUNG KYU KWON
  • Patent number: 9665122
    Abstract: A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 30, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung Kyu Kwon, Hae Gu Lee, Byeong Yeon Cho
  • Patent number: 9640499
    Abstract: A semiconductor chip may include a semiconductor substrate, a first central pad, a second central pad, a first peripheral pad, a second peripheral pad, a first pad line and a second pad line. The semiconductor substrate may have an active face. The first central pad and the second central pad may be arranged on a central region of the active face. The first peripheral pad and the second peripheral pad may be arranged on an edge region of the active face. The first pad line may be connected between the first central pad and the first peripheral pad. The second pad line may be connected between the second central pad and the second peripheral pad.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Heung Kyu Kwon
  • Patent number: 9601458
    Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Su-chang Lee
  • Publication number: 20170068633
    Abstract: A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventor: HEUNG KYU KWON
  • Publication number: 20170012025
    Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu KWON, Jong-Kook KIM, Ji-Chul KIM, Byeong-Yeon CHO
  • Publication number: 20160358893
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu KWON, Min-Ok NA, Sung-Woo PARK, Ji-Hyun PARK, Su-Min PARK
  • Publication number: 20160284655
    Abstract: A semiconductor chip may include a semiconductor substrate, a first central pad, a second central pad, a first peripheral pad, a second peripheral pad, a first pad line and a second pad line. The semiconductor substrate may have an active face. The first central pad and the second central pad may be arranged on a central region of the active face. The first peripheral pad and the second peripheral pad may be arranged on an edge region of the active face. The first pad line may be connected between the first central pad and the first peripheral pad. The second pad line may be connected between the second central pad and the second peripheral pad.
    Type: Application
    Filed: February 17, 2016
    Publication date: September 29, 2016
    Inventor: Heung Kyu KWON
  • Publication number: 20160161992
    Abstract: A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 9, 2016
    Inventor: Heung Kyu KWON
  • Publication number: 20160113115
    Abstract: A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.
    Type: Application
    Filed: July 7, 2015
    Publication date: April 21, 2016
    Inventors: HEUNG KYU KWON, KYOUNG MOOK LIM