Patents by Inventor Hey Lee

Hey Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10626303
    Abstract: Provided are an adhesive sheet including a base layer, an adhesive layer, and a release paper, which are sequentially disposed, the adhesive layer being attached to a target for attachment after the release paper is removed, wherein the adhesive layer includes a first adhesive layer, which is attached to one surface of the base layer, and second adhesive layers attached to the first adhesive layer and to the release paper, the second adhesive layers being arranged so as to form a pattern, wherein the second adhesive layers remain attached to the target for attachment, wherein a film is attached to the target for attachment without requiring the film to be wet with water, and wherein an air layer or air bubbles are discharged from the adhesive sheet through paths that serve to discharge the air bubbles, thereby preventing a reduction of initial adhesive force, solving a problem of freezing, and achieving easy attachment, and a method of manufacturing the same.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 21, 2020
    Assignee: SMART CO., LTD.
    Inventors: Sung Je Kim, Wang Je Kim, Jung Hey Lee
  • Patent number: 10256251
    Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: April 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun-Seok Choi, Sa-Yong Shim, In-Hey Lee, Sung-Wook Jung, Jung-Seok Oh
  • Publication number: 20190077995
    Abstract: Provided are an adhesive sheet including a base layer, an adhesive layer, and a release paper, which are sequentially disposed, the adhesive layer being attached to a target for attachment after the release paper is removed, wherein the adhesive layer includes a first adhesive layer, which is attached to one surface of the base layer, and second adhesive layers attached to the first adhesive layer and to the release paper, the second adhesive layers being arranged so as to form a pattern, wherein the second adhesive layers remain attached to the target for attachment, wherein a film is attached to the target for attachment without requiring the film to be wet with water, and wherein an air layer or air bubbles are discharged from the adhesive sheet through paths that serve to discharge the air bubbles, thereby preventing a reduction of initial adhesive force, solving a problem of freezing, and achieving easy attachment, and a method of manufacturing the same.
    Type: Application
    Filed: December 27, 2017
    Publication date: March 14, 2019
    Inventors: Sung Je KIM, Wang Je KIM, Jung Hey LEE
  • Publication number: 20180047748
    Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Eun-Seok CHOI, Sa-Yong SHIM, In-Hey LEE, Sung-Wook JUNG, Jung-Seok OH
  • Patent number: 9831264
    Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: November 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Eun-Seok Choi, Sa-Yong Shim, In-Hey Lee, Sung-Wook Jung, Jung-Seok Oh
  • Publication number: 20160181275
    Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Inventors: Eun-Seok CHOI, Sa-Yong SHIM, In-Hey LEE, Sung-Wook JUNG, Jung-Seok OH
  • Patent number: 9306040
    Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: April 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Eun-Seok Choi, Sa-Yong Shim, In-Hey Lee, Sung-Wook Jung, Jung-Seok Oh
  • Patent number: 9023702
    Abstract: A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: In-Hey Lee
  • Publication number: 20140357031
    Abstract: A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Inventor: In-Hey LEE
  • Publication number: 20140299931
    Abstract: A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
    Type: Application
    Filed: July 17, 2013
    Publication date: October 9, 2014
    Inventors: Eun-Seok CHOI, Sa-Yong SHIM, In-Hey LEE, Sung-Wook JUNG, Jung-Seok OH
  • Patent number: 8836013
    Abstract: A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: In-Hey Lee
  • Patent number: 8717814
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the planar channel layers.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 6, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sang Moo Choi, In Hey Lee
  • Publication number: 20140042519
    Abstract: A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.
    Type: Application
    Filed: December 17, 2012
    Publication date: February 13, 2014
    Applicant: SK hynix Inc.
    Inventor: In-Hey LEE
  • Publication number: 20130100741
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel to the substrate, and gate insulating layers formed over the planar channel layers.
    Type: Application
    Filed: August 30, 2012
    Publication date: April 25, 2013
    Inventors: Sang Moo CHOI, In Hey LEE
  • Publication number: 20120273865
    Abstract: A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Inventors: In Hey LEE, Byung Soo PARK, Sang Hyun OH, Sun Mi PARK
  • Patent number: 5454788
    Abstract: A balloon catheter includes a flexible small-diameter guide wire provided with an enlarged-diameter distal end portion, and a flexible elongated tubular shaft with at least one dual-function fluid-conducting lumen adapted to both receive the guide wire extending therethrough, and to communicate pressurized inflation fluid to a distal balloon of the catheter. A distal orifice of the catheter communicates with the balloon and is provided with selective valving means for releasably engaging sealingly with the enlarged distal end portion of the guide wire. Apparatus is disclosed for axially moving the guide wire to effect engagement and disengagement of the enlarged distal end portion with the selective valving means of the catheter shaft. A torquer device is also provided by means of which the guide wire may be rotated relative to the catheter shaft for steering of the guide wire along a vascular pathway.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: October 3, 1995
    Assignee: Baxter International Inc.
    Inventors: Blair Walker, Manouchehr Miraki, William Rice, Kambiz Ghaerzadeh, Brett Trauthen, Hey Lee, Greg Welsh, Henry Nita, Shawn O'Leary, Mark Dehdashtian, Sheryl W. Higgins, Nora Pham