Patents by Inventor Heyun H. Liu

Heyun H. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6963564
    Abstract: A network (4) includes optical routers (19), which route information in fibers (10). Each fiber carries a plurality of data channels (16), carrying data in data bursts (28) and a control channel, carrying control information in burst header packets (32). A burst header packet includes routing information for an associated data burst (28) and precedes its associated data burst. Information on the data channels and control channel is organized in synchronized slots. Multiple burst header packets occupy portions of a slot, referred to as micro-slots. When the burst header packets are received, an egress processor (52) schedules the routing of their associated bursts. The egress processor (52) determines a time at which a data burst can be scheduled for passing through an optical matrix (40) to the desired output channel group (the burst can be delayed via fiber delay lines (46) if necessary).
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: November 8, 2005
    Assignee: Alcatel
    Inventor: Heyun H. Liu
  • Publication number: 20020154360
    Abstract: A network (4) includes optical routers (19), which route information in fibers (10). Each fiber carries a plurality of data channels (16), carrying data in data bursts (28) and a control channel, carrying control information in burst header packets (32). A burst header packet includes routing information for an associated data burst (28) and precedes its associated data burst. Information on the data channels and control channel is organized in synchronized slots. Multiple burst header packets occupy portions of a slot, referred to as micro-slots. When the burst header packets are received, an egress processor (52) schedules the routing of their associated bursts. The egress processor (52) determines a time at which a data burst can be scheduled for passing through an optical matrix (40) to the desired output channel group (the burst can be delayed via fiber delay lines (46) if necessary).
    Type: Application
    Filed: February 26, 2001
    Publication date: October 24, 2002
    Inventor: Heyun H. Liu
  • Publication number: 20020149820
    Abstract: A network (4) includes optical routers (19), which route information in fibers (10). Each fiber carries a plurality of data channels (16), carrying data in data bursts (28) and a control channel, carrying control information in burst header packets (32). A burst header packet includes routing information for an associated data burst (28) and precedes its associated data burst. Information on the data channels and control channel is organized in synchronized slots. Multiple burst header packets occupy portions of a slot, referred to as micro-slots. When the burst header packets are received, an egress processor (52) schedules the routing of their associated bursts. The egress processor (52) determines a time at which a data burst can be scheduled for passing through an optical matrix (40) to the desired output channel group (the burst can be delayed via fiber delay lines (46) if necessary).
    Type: Application
    Filed: February 26, 2001
    Publication date: October 17, 2002
    Inventor: Heyun H. Liu
  • Publication number: 20020118420
    Abstract: A network (4) includes optical routers (19), which route information in fibers (10). Each fiber carries a plurality of data channels (16), carrying data in data bursts (28) and a control channel, carrying control information in burst header packets (32). A burst header packet includes routing information for an associated data burst (28) and precedes its associated data burst. Information on the data channels and control channel is organized in synchronized slots. Multiple burst header packets occupy portions of a slot, referred to as micro-slots. When the burst header packets are received, an egress processor (52) schedules the routing of their associated bursts. The egress processor (52) determines a time at which a data burst can be scheduled for passing through an optical matrix (40) to the desired output channel group (the burst can be delayed via fiber delay lines (46) if necessary).
    Type: Application
    Filed: December 18, 2001
    Publication date: August 29, 2002
    Inventor: Heyun H. Liu