Abstract: Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance.

Abstract: Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance.

Abstract: A semiconductor memory device includes: a driving voltage supplying unit configured to detect a simultaneous activation of banks and selectively supply one of a high voltage and an external voltage lower than the high voltage as a driving voltage; a flag detecting unit configured to detect inputs of flag signals activated in response to an active command and generate a precharge control signal; and a signal generating unit configured to generate a bit line precharge signal swinging between the driving voltage and a ground voltage in response to the precharge control signal.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A semiconductor memory device includes an address latch unit, a decoding circuit, and a precharge control unit. The address latch unit provides a latched address during an active operation interval and a precharge operation interval. The decoding circuit decodes an output of the address latch unit to provide a decoded signal to activate a word line arranged in a data storage area. The precharge control unit controls the decoded signal to be disabled during the precharge operation interval.

Abstract: A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals.

Abstract: A voltage generating circuit of a semiconductor memory apparatus is provided including a voltage generator that generates a core voltage in response to a voltage generating signal, a voltage drop part that drops a level of the core voltage to a predetermined target level when the level of the core voltage is increased by an overdrive operation, and a voltage generation controller that disables the voltage generating signal when the overdrive operation is performed so as to stop the driving of the voltage generator.

Abstract: A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.

Abstract: A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self-refresh driving device includes a first reference voltage generating unit for generating a reference voltage robust to temperature, the first reference voltage generating means being formed with a plurality of MOS transistors, the number of source contacts of the MOS transistors being adjusted such that variation of saturation current through source-drain is compensated for; a second reference voltage generating unit for generating a second reference voltage sensitive to temperature; a level comparator for comparing the first reference voltage with the second reference voltage; and an oscillator for generating a clock signals having differing period depending on the output signal of the level comparator.

Abstract: A semiconductor memory device controls the voltage level of an equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD, when the equalization signal is repeated by a repeater. In order to improve bit line precharging performance of the bit line precharge portion enabled by the equalization signal, a rising interval of the equalization signal is activated as the boost voltage. Precharging is then performed with the external supply voltage after a predetermined time period. Thus, a thin gate insulating membrane can be used in a transistor in the bit line precharge portion which receives the equalization signal can be formed.

Abstract: A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals.

Abstract: A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal.

Abstract: A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier. The first and the second pull-down voltages are used in different driving periods to protect data from noises caused by another memory bank. A driving period can be separated into an initial sensing period, wherein large currents are consumed and significant noise is generated, and a subsequent stable period. The driving period can be separated into a pre-precharge period and a post-precharge period.

Abstract: A semiconductor memory device includes: a driving voltage supplying unit configured to detect a simultaneous activation of banks and selectively supply one of a high voltage and an external voltage lower than the high voltage as a driving voltage; a flag detecting unit configured to detect inputs of flag signals activated in response to an active command and generate a precharge control signal; and a signal generating unit configured to generate a bit line precharge signal swinging between the driving voltage and a ground voltage in response to the precharge control signal.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A voltage generating circuit of a semiconductor memory apparatus is provided including a voltage generator that generates a core voltage in response to a voltage generating signal, a voltage drop part that drops a level of the core voltage to a predetermined target level when the level of the core voltage is increased by an overdrive operation, and a voltage generation controller that disables the voltage generating signal when the overdrive operation is performed so as to stop the driving of the voltage generator.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active command. The bit line over driving control signal generator for use in a semiconductor memory device includes a delaying unit for delaying an over driving signal generated in response to an active command to thereby output a delayed over driving signal, a controlling unit for determining whether the delayed over driving signal is outputted without any modification or outputted with being disabled in response to the over driving signal, a read command, and a precharge command, and a pulse width adding unit for adding a predetermined pulse width of the delayed over driving signal to the over driving signal to thereby output a bit line over driving control signal.

Abstract: A metal oxide semiconductor (MOS) transistor includes a source region having at least one source contact; a drain region having at least one drain contact; and a gate provided between the source region and the drain region, wherein the number of source contacts included in the source region is different from the number of drain contacts included in the source region.

Abstract: A digital temperature sensing device uses temperature depending characteristic of contact resistance of a MOS transistor and a self-refresh driving device adjusts its self-refresh period depending on temperature using the digital temperature sensing device. The self-refresh driving device includes a first reference voltage generating unit for generating a reference voltage robust to temperature, the first reference voltage generating means being formed with a plurality of MOS transistors, the number of source contacts of the MOS transistors being adjusted such that variation of saturation current through source-drain is compensated for; a second reference voltage generating unit for generating a second reference voltage sensitive to temperature; a level comparator for comparing the first reference voltage with the second reference voltage; and an oscillator for generating a clock signals having differing period depending on the output signal of the level comparator.