Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

Abstract: A communication system, a communication apparatus, and an electronic appliance are provide. The communication system, a communication apparatus and an electronic appliance can operate at a high data transfer rate without raising the frequency of the data transfer clock. In a communication apparatus, which is a card-shaped semiconductor memory apparatus, eleventh, twelfth, thirteenth and fourteenth belt-like terminals T (T11, T12, T13 and T14) are provided in addition to the third, fourth, fifth and seventh belt-like terminals T (T3, T4, T5 and T7) arranged at an end of the cabinet as terminals for transmitting data to and receiving data from a digital still camera. With this arrangement, the number of terminals that can be used for exchanging data with the digital still camera is increased from four to eight to make it possible to improve the data transfer rate without raising the frequency of the data transfer clock.

Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Abstract: In a memory card with a newly-added module for performing data communication, data communication is stably performed without receiving a noise effect. As an embodiment of the present invention, a memory card 100 has a thin-plate-shaped holding member 20, a memory section 24 provided as buried in the holding member 20, plural first connection pieces 2-10 connected to the memory section 24, a data communication section 26 provided as buried in the holding member 20, and two connection pieces 11, 12 connected to the data communication section 26. The two second connection pieces 11, 12 are disposed at the end of a row part R1 on which only the plural first connection pieces 2-10 are aligned. One first connection piece 10 positioned at the end of the row part R1 is a ground terminal. That is to say, in the plural first connection pieces 2-10, the first connection piece 10 adjacent to the second connection piece 11 is a ground terminal.

Abstract: A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: A memory card (1) is provided with data terminals (DATA0/SDIO, DATA1, DATA2, DATA3) for making two-way communication of 4-bit parallel data with a host apparatus on four data communication lines, a clock terminal (SCLK) for receiving a clock from the host apparatus, and a terminal (BS) for receiving, from the host apparatus, a bus-state signal indicating the states of the 4-bit parallel data communication lines and transfer start timing. The first data terminal (DATA0/SDIO) is used as a data terminal for a memory card intended for 1-bit data communication to maintain the compatibility with this memory card.

Abstract: A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: This invention is an information processing device such as a computer, as a host device, and a memory card as an external connection device to be connected to the host device. A memory card (1) and a host device (2) are connected with each other in accordance with a six-wire-system half-duplex protocol using four-bit parallel signals, a bus state signal, and a clock signal. When the state of the bus state signal is a state of accepting interruption, the memory card (1) sends an interrupt signal (INT) to four-bit parallel buses. Different elements of interruption are allocated to the respective bits of the four-bit parallel signals. That is, the bit at which the INT signal is sent varies depending on the content of interruption.

Abstract: In a memory card with a newly-added module for performing data communication, data communication is stably performed without receiving a noise effect. As an embodiment of the present invention, a memory card 100 has a thin-plate-shaped holding member 20, a memory section 24 provided as buried in the holding member 20, plural first connection pieces 2-10 connected to the memory section 24, a data communication section 26 provided as buried in the holding member 20, and two connection pieces 11, 12 connected to the data communication section 26. The two second connection pieces 11, 12 are disposed at the end of a row part R1 on which only the plural first connection pieces 2-10 are aligned. One first connection piece 10 positioned at the end of the row part R1 is a ground terminal. That is to say, in the plural first connection pieces 2-10, the first connection piece 10 adjacent to the second connection piece 11 is a ground terminal.

Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Abstract: An interface is connectable between a main unit and an IC card and includes a data transmission path and a clock signal transmission path. The IC card receives a clock signal transmitted from the main unit over the clock signal transmission path and returns the clock signal to the main unit over the clock signal transmission path. A data transmission unit of the IC card receives the clock signal and outputs data over the data transmission path for delivery to the main unit. A data receiving unit of the main unit receives the returned clock signal and receives the data transmitted by the data transmission unit.

Abstract: A communication system, a communication apparatus, and an electronic appliance are provide. The communication system, a communication apparatus and an electronic appliance can operate at a high data transfer rate without raising the frequency of the data transfer clock. In a communication apparatus, which is a card-shaped semiconductor memory apparatus, eleventh, twelfth, thirteenth and fourteenth belt-like terminals T (T11, T12, T13 and T14) are provided in addition to the third, fourth, fifth and seventh belt-like terminals T (T3, T4, T5 and T7) arranged at an end of the cabinet as terminals for transmitting data to and receiving data from a digital still camera. With this arrangement, the number of terminals that can be used for exchanging data with the digital still camera is increased from four to eight to make it possible to improve the data transfer rate without raising the frequency of the data transfer clock.

Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

Abstract: Drinking straw (1) for drinks, which is made of a material which includes one or more polyolefins, which polyolefin or which polyolefins include one or more inorganic filler materials. The invention is also directed towards the use of such a material in drinking straws for drinks.

Abstract: When data is transmitted from a main unit of an apparatus 11 to an IC card 12, a clock signal is input to a clock input of FF2R through a path of (buffer CK1S→transmission path CLK→buffer CK2R). A data signal is output from FF1S in synchronization with a leading edge of the clock signal. The data signal is input to a data input of FF2R through a path of (buffer 101S→transmission path DATA→buffer 102R). Thereafter, the data signal is captured. When data is transmitted from the IC card 12 to the main body 11, a clock signal is input to a clock input of FF1R through a path of (buffer CK2S→transmission path CLK→buffer CK1R). The data signal is output from FF2S in synchronization with a leading edge of the clock signal. The clock signal is input to a data input of FF1R through a path of (buffer 102S→transmission path DATA→buffer 101R). Thereafter, the data signal is captured.

Abstract: A memory card (1) is provided with data terminals (DATA0/SDIO, DATA1, DATA2, DATA3) for making two-way communication of 4-bit parallel data with a host apparatus on four data communication lines, a clock terminal (SCLK) for receiving a clock from the host apparatus, and a terminal (BS) for receiving, from the host apparatus, a bus-state signal indicating the states of the 4-bit parallel data communication lines and transfer start timing. The first data terminal (DATA0/SDIO) is used as a data terminal for a memory card intended for 1-bit data communication to maintain the compatibility with this memory card.

Abstract: A threaded member projecting from a press slide includes a projection on its upper end. A motor raises and lowers the threaded member in tandem with a slide adjustment mechanism. A plate disposed on a lower surface of a press crown is moved to slidably enclose the projection. The press slide is locked when the lower surface of the projection and the upper surface of the plate abut each other.