Abstract: In a time division multiplex transferring system which uses fixed setting, on-demand, and frame relay bandwidths, a first time switch allocates the on-demand and frame relay bandwidths in response to a first allocation setting datum to produce two output signals. A second time switch allocates the on-demand and frame relay bandwidths in response to a second allocation setting datum to produce two output signals. A bandwidth allocation controlling device produces and renews the first and second allocation setting data in response to the connectivity restriction to produce and transmit a first allocation change datum to a counter node. The bandwidth allocation controlling device thereafter produces a first allocation end signal in response to a second allocation end signal from the counter node.

Abstract: For switching data time slots between input and output data signals, each having a multiframe structure, a time slot switching device comprises only one time slot switching circuit. Consequently, the device comprises a sole data memory, a single novel write address generator, and only one novel read address generator. The write address generator comprises first through N-th frame synchronization units, where N represents the number of attributes by which the data time slots are featured. Connected to the frame synchronization units, a selector is controlled by a switch mode memory (SWM) controlled, in turn, by a central processing unit. Like each conventional read address generator, the novel read address generator comprises an address control memory (ACM) controlled by the central processing unit. Only one phase adjusting circuit is used to adjust operation of the read address generator relative to that of the write address generator as regards phases of operation.

Abstract: According to this invention, a time slot switching function diagnostic system includes a first inserting circuit, a data memory, an address controller, a second inserting circuit, and a check circuit. The first inserting circuit inserts path monitoring test pattern data into a specific on-line time slot of a unit frame consisting of N time slots. The data memory writes and reads data input to the time slots. The address control circuit supplies write and read addresses to the data memory. The second inserting circuit feeds back an output from the data memory to an input side to repetitively insert the test pattern data in time slots sequentially following the specific time slot. The check circuit extracts the test pattern data from an output corresponding to an Nth time slot of the data memory to check the test pattern data.