Patents by Inventor Hideaki Furukawa
Hideaki Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974444Abstract: There is provided a solid-state image sensor, a solid-state imaging device, an electronic apparatus, and a method of manufacturing a solid-state image sensor capable of improving characteristics. There is provided a solid-state image sensor including a stacked structure that includes a semiconductor substrate, a first photoelectric converter provided above the semiconductor substrate and converting light into charges, and a second photoelectric converter provided above the first photoelectric converter and converting light into charges, where the first photoelectric converter and the second photoelectric converter include a photoelectric conversion stacked structure in which a common electrode, a photoelectric conversion film, and a readout electrode are stacked so that the first photoelectric converter and the second photoelectric converter are in a line-symmetrical relationship with each other with a vertical plane perpendicular to a stacking direction of the stacked structure as an axis of symmetry.Type: GrantFiled: June 11, 2019Date of Patent: April 30, 2024Assignees: SONY CORPORATION, SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hideaki Togashi, Iwao Yagi, Masahiro Joei, Fumihiko Koga, Kenichi Murata, Shintarou Hirata, Yosuke Saito, Akira Furukawa
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Publication number: 20240096914Abstract: Provided is an imaging element including a photoelectric conversion unit formed by stacking a first electrode, a photoelectric conversion layer and a second electrode. The photoelectric conversion unit further includes a charge storage electrode which is disposed to be spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer via an insulating layer. The photoelectric conversion unit is formed of N number of photoelectric conversion unit segments, and the same applies to the photoelectric conversion layer, the insulating layer and the charge storage electrode. An nth photoelectric conversion unit segment is formed of an nth charge storage electrode segment, an nth insulating layer segment and an nth photoelectric conversion layer segment. As n increases, the nth photoelectric conversion unit segment is located farther from the first electrode. A thickness of the insulating layer segment gradually changes from a first to Nth photoelectric conversion unit segment.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: SONY GROUP CORPORATIONInventors: Akira FURUKAWA, Yoshihiro ANDO, Hideaki TOGASHI, Fumihiko KOGA
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Publication number: 20220113944Abstract: In an arithmetic processing device, a controller includes: a second non-linear converter that, when a selector has branched off to a second processing side, performs non-linear arithmetic processing on the result of a cumulative addition processing of a first adder; and a second pooling processing part to which the results of the cumulative addition processing of k first adders that have been subject to the non-linear arithmetic processing by the second non-linear converter are inputted, the second pooling processing part performing a pooling process on the simultaneously inputted data. A data-storing memory manager writes the same data to k different data-storing memories when the number of input feature map data is less than or equal to N/k. The controller performs a control so that the selector branches off to the second processing side when the number of input feature map data is less than or equal to N/k.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Applicant: OLYMPUS CORPORATIONInventor: Hideaki Furukawa
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Publication number: 20210182656Abstract: In this arithmetic processing device, during a filter processing and a cumulative addition processing for calculating a specific pixel of an output feature amount map, an arithmetic controller controls so as to temporarily store an intermediate result in a cumulative addition result storing memory and process another pixel, store the intermediate result of the cumulative addition processing for all pixels in the cumulative addition result storing memory, then return to a first pixel, read the value stored in the cumulative addition result storing memory as an initial value of the cumulative addition processing, and continue the cumulative addition processing.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Applicant: OLYMPUS CORPORATIONInventor: Hideaki Furukawa
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Publication number: 20210117762Abstract: An SRAM write controller of an arithmetic processing device for deep learning, which performs a convolution processing and a full-connect processing, virtually divides each SRAM constituting a data storage memory into a plurality of areas, switches the area to be written by the ID and controls so that different input feature maps of the same coordinate are stored in the same SRAM, and controls such that different input feature value map data of the same coordinate is stored in the same SRAM.Type: ApplicationFiled: December 23, 2020Publication date: April 22, 2021Applicant: OLYMPUS CORPORATIONInventor: Hideaki Furukawa
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Publication number: 20210042616Abstract: An arithmetic part of an arithmetic processing device includes: a filter processing part that has a multiplier and a first adder and performs filter processing; a second adder that performs cumulative addition processing that cumulatively adds all of the results of the filter processing as executed in N parallel; a non-linear conversion part that performs non-linear arithmetic processing on the result of the cumulative addition processing; a pooling processing part that performs pooling processing on the result of the non-linear arithmetic processing; and an arithmetic control part that controls the filter processing part, the second adder, the non-linear conversion part, and the pooling processing part.Type: ApplicationFiled: October 27, 2020Publication date: February 11, 2021Applicant: OLYMPUS CORPORATIONInventor: Hideaki Furukawa
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Patent number: 9961420Abstract: [Problem] To provide an optical packet buffer control device, without making device construction large in scale, that is capable of dynamically responding to traffic and suppressing power consumption.Type: GrantFiled: January 19, 2015Date of Patent: May 1, 2018Assignee: National Institute of Information and Communications TechnologyInventors: Takahiro Hirayama, Hideaki Furukawa
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Patent number: 9787905Abstract: An image processing apparatus receives an image signal and generates a display image having an image range associated with a display area of a display unit from an image based on the image signal. The image processing apparatus includes a position-of-interest-calculating-unit, a frame-out-accuracy-calculation-unit, an alteration-variable-decision-unit and an image-alteration-unit. The position-of-interest-calculating-unit calculates a position of interest as a position of an object of interest in the image. The frame-out-accuracy-calculation-unit calculates a frame-out accuracy representing an accuracy that the position of interest deviates from the image range based on the position of interest and the image range. The alteration-variable-decision-unit decides a processing variable of alteration processing performed with respect to the image in conformity with the frame-out accuracy.Type: GrantFiled: May 18, 2015Date of Patent: October 10, 2017Assignee: OLYMPUS CORPORATIONInventors: Nobuyuki Watanabe, Naoyuki Miyashita, Hideaki Furukawa, Hiroshi Matsuzaki, Takahiro Yano
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Publication number: 20170013332Abstract: [Problem] To provide an optical packet buffer control device, without making device construction large in scale, that is capable of dynamically responding to traffic and suppressing power consumption.Type: ApplicationFiled: January 19, 2015Publication date: January 12, 2017Inventors: Takahiro HIRAYAMA, Hideaki FURUKAWA
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Publication number: 20150249790Abstract: An image processing apparatus receives an image signal and generates a display image having an image range associated with a display area of a display unit from an image based on the image signal. The image processing apparatus includes a position-of-interest-calculating-unit, a frame-out-accuracy-calculation-unit, an alteration-variable-decision-unit and an image-alteration-unit. The position-of-interest-calculating-unit calculates a position of interest as a position of an object of interest in the image. The frame-out-accuracy-calculation-unit calculates a frame-out accuracy representing an accuracy that the position of interest deviates from the image range based on the position of interest and the image range. The alteration-variable-decision-unit decides a processing variable of alteration processing performed with respect to the image in conformity with the frame-out accuracy.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Applicant: OLYMPUS CORPORATIONInventors: Nobuyuki WATANABE, Naoyuki Miyashita, Hideaki Furukawa, Hiroshi Matsuzaki, Takahiro Yano
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Publication number: 20150220374Abstract: An information processing apparatus comprises: a first platform having a first application programming interface; a wrapper absorbing difference between the first application programming interface and a second application programming interface on a second platform having the second application programming interface; and an intermediate task capable of calling a system call of the first platform and a system call of the wrapper, wherein when the intermediate task makes communication with a first task that is a task generated on the first platform, the intermediate task uses the system call of the first platform, whereas when the intermediate task makes communication with a second task that is a task generated on the wrapper, the intermediate task uses the system call of the wrapper.Type: ApplicationFiled: February 2, 2015Publication date: August 6, 2015Applicant: RICOH COMPANY, LIMITEDInventors: Taiki TSUZUKI, Hideaki FURUKAWA, Naoki HADACHI, Shingo YAMAZAKI
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Patent number: 9019591Abstract: It is an object of the present invention to provide a rare earth doped fiber whose transient response is suppressed and an optical amplifier for optical packet communication having a good characteristic even if there is little traffic. The above-mentioned problem is solved by an optical amplifier for optical packet communication comprising a first rare earth doped fiber (EDFA) having an active region whose diameter is between 3.4 ?m and 10 ?m, inclusive, an intermediate gain equalizing filter, and a second EDF, wherein the first EDFA is shorter than the second EDFA, and wherein the intermediate gain equalizing filter adjusts the intensity of each wavelength channel so as to equalize the light intensity of each wavelength channel having transmitted through the second EDF.Type: GrantFiled: March 12, 2008Date of Patent: April 28, 2015Assignees: National Institute of Information and communications Technology, Amonics LimitedInventors: Yoshinari Awaji, Hideaki Furukawa, Naoya Wada, Ray Man, Peter Chan, Eddie Kong
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Patent number: 8904069Abstract: A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed.Type: GrantFiled: October 28, 2011Date of Patent: December 2, 2014Assignee: Olympus CorporationInventors: Yoshinobu Tanaka, Keisuke Nakazono, Akira Ueno, Hideaki Furukawa
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Patent number: 8745623Abstract: An information processing apparatus includes an application and functional modules configured to collaborate with each other to provide an application function of the application. Each of the functional modules operates as a requester that requests a provider function and a provider that provides the provider function requested by the requester. Each of the functional modules includes a function availability query unit that, at the requester, queries the provider about whether the requested provider function is available, a function availability response unit that, at the provider, sends a response indicating whether the requested provider function is available to the requester, and a function execution determining unit that, at the requester, controls execution of a requester function of the requester based on the response sent from the function availability response unit.Type: GrantFiled: September 21, 2011Date of Patent: June 3, 2014Assignee: Ricoh Company, Ltd.Inventors: Koutarou Shibata, Hideaki Furukawa
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Publication number: 20120113307Abstract: An image processing apparatus receives an image signal and generates a display image having an image range associated with a display area of a display unit from an image based on the image signal. The image processing apparatus includes a position-of-interest-calculating-unit, a frame-out-accuracy-calculation-unit, an alteration-variable-decision-unit and an image-alteration-unit. The position-of-interest-calculating-unit calculates a position of interest as a position of an object of interest in the image. The frame-out-accuracy-calculation-unit calculates a frame-out accuracy representing an accuracy that the position of interest deviates from the image range based on the position of interest and the image range. The alteration-variable-decision-unit decides a processing variable of alteration processing performed with respect to the image in conformity with the frame-out accuracy.Type: ApplicationFiled: November 2, 2011Publication date: May 10, 2012Applicant: OLYMPUS CORPORATIONInventors: Nobuyuki Watanabe, Naoyuki Miyashita, Hideaki Furukawa, Hiroshi Matsuzaki, Takahiro Yano
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Publication number: 20120110224Abstract: A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed.Type: ApplicationFiled: October 28, 2011Publication date: May 3, 2012Applicant: OLYMPUS CORPORATIONInventors: Yoshinobu Tanaka, Keisuke Nakazono, Akira Ueno, Hideaki Furukawa
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Publication number: 20120096464Abstract: An information processing apparatus includes an application and functional modules configured to collaborate with each other to provide an application function of the application. Each of the functional modules operates as a requester that requests a provider function and a provider that provides the provider function requested by the requester. Each of the functional modules includes a function availability query unit that, at the requester, queries the provider about whether the requested provider function is available, a function availability response unit that, at the provider, sends a response indicating whether the requested provider function is available to the requester, and a function execution determining unit that, at the requester, controls execution of a requester function of the requester based on the response sent from the function availability response unit.Type: ApplicationFiled: September 21, 2011Publication date: April 19, 2012Applicant: RICOH COMPANY, LTD.Inventors: Koutarou SHIBATA, Hideaki FURUKAWA
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Patent number: D752127Type: GrantFiled: March 11, 2015Date of Patent: March 22, 2016Assignee: FURYU CORPORATIONInventors: Ryoko Inagaki, Hideaki Furukawa, Shingo Hamaguchi, Sadayasu Araki, Tsuneo Okada, Wakako Sakahara, Michiyo Wakayoshi
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Patent number: D807943Type: GrantFiled: January 29, 2016Date of Patent: January 16, 2018Assignee: FURYU CORPORATIONInventors: Ryoko Inagaki, Hideaki Furukawa, Shingo Hamaguchi, Sadayasu Araki, Tsuneo Okada, Wakako Sakahara, Michiyo Wakayoshi
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Patent number: D846621Type: GrantFiled: December 4, 2017Date of Patent: April 23, 2019Assignee: FURYU CORPORATIONInventors: Ryoko Inagaki, Hideaki Furukawa, Shingo Hamaguchi, Sadayasu Araki, Tsuneo Okada, Wakako Sakahara, Michiyo Wakayoshi